 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| siuc-x single chip isdn usb controller psb 2154 version 1.3 data sheet, ds 1, jan. 2001 wired communications never stop thinking.
edition 2001-01-24 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications siuc-x single chip isdn usb controller psb 2154 version 1.3 data sheet, ds 1, jan. 2001 never stop thinking. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com psb 2154 revision history: 2001-01-24 ds 1 previous version: page subjects (major changes since last revision) psb 2154 table of contents page data sheet 2001-01-24 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 pin states in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 c800 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.1 external memory address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.3 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.4 general purpose registers - overview . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.5 special function registers - overview . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3 external bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.1 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.2 shared and separate external memories . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3 switching of control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.4 enabling of xram access and memory ports / signals . . . . . . . . . . . . 42 3.3.5 partitioning of ram, switching from rom to ram . . . . . . . . . . . . . . . . 43 3.3.6 external bus interface during emulation . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.7 port structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 enhanced hooks emulation concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5 timer 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.6 timer 0 and 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6.1 tlx / thx - timer low / high registers . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6.2 tcon - timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.6.3 tmod - timer mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.7 microcontroller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7.1 dpsel - data pointer select register . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7.2 data pointer register low / high - dpl / dph . . . . . . . . . . . . . . . . . . . 61 3.7.3 pcon - power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7.4 psw - program status word register . . . . . . . . . . . . . . . . . . . . . . . . . 63 psb 2154 table of contents page data sheet 2001-01-24 3.7.5 wcon - wakeup control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.7.6 hcon - hardware configuration register . . . . . . . . . . . . . . . . . . . . . . 65 3.7.7 plcona/b - pll configuration registers a, b . . . . . . . . . . . . . . . . . . . 66 3.7.8 acc / b - accumulator / b register . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.7.9 psiz - program ram size register . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.7.10 dsiz - data ram size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.7.11 syscon1 - system control register 1 . . . . . . . . . . . . . . . . . . . . . . . . 71 3.7.12 syscon2 - system control register 2 . . . . . . . . . . . . . . . . . . . . . . . . 73 3.7.13 xpage - xram page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4 usb module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1 transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2 memory buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.2.2 single buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.2.2.1 usb write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.2.2.2 usb read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2.3 dual buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.2.4 buffer underrun / overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.3 memory buffer organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4 memory buffer address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5 usb initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.6 usb device framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.1 enumeration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.2 control transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.2.1 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.2.2 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.6.2.3 status stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6.3 standard device requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.7 onchip usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.8 detach / attach detection and usb power modes . . . . . . . . . . . . . . . . . 102 4.8.1 self-powered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.8.2 bus-powered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.9 usb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.9.1 gesr- global endpoint stall register . . . . . . . . . . . . . . . . . . . . . . . . 107 4.9.2 epsel - endpoint select register . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.9.3 ifcsel - interface select register . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.9.4 usbval - usb data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.9.5 adroff - address offset register . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.9.6 ciar - configuration request register . . . . . . . . . . . . . . . . . . . . . . . 112 4.9.7 dcr - device control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.9.8 dpwdr - device power down register . . . . . . . . . . . . . . . . . . . . . . 115 4.9.9 fnrh / fnrl - frame number register high / low byte . . . . . . . . . 116 psb 2154 table of contents page data sheet 2001-01-24 4.9.10 dgsr - device get_status register . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.9.11 igsr - interface get_status register . . . . . . . . . . . . . . . . . . . . . . . . 118 4.9.12 epbcn - endpoint buffer control register . . . . . . . . . . . . . . . . . . . . . 119 4.9.13 epbsn - endpoint buffer status register . . . . . . . . . . . . . . . . . . . . . . 120 4.9.14 epban - endpoint base address register . . . . . . . . . . . . . . . . . . . . . 122 4.9.15 eplenn - endpoint buffer length register . . . . . . . . . . . . . . . . . . . . 123 4.9.16 egsr - endpoint get_status register . . . . . . . . . . . . . . . . . . . . . . . . 124 5 isdn module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.1 general functions and architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.1.1 timer 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.2 activation indication via pin acl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.2 s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.2.1 s/t-interface coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.2.2 s/t-interface multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2.3 multiframe synchronization (m-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.4 data transfer and delay between iom-2 and s/t . . . . . . . . . . . . . . . 136 5.2.5 transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.2.6 receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.2.7 s/t interface circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.2.7.1 external protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.2.8 s/t interface delay compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.2.9 level detection power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 5.2.10 transceiver enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.2.11 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.3 control of layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.1 state machine te mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3.1.1 state transition diagram (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3.1.2 states (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3.1.3 c/i codes (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.1.4 infos on s/t (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.3.2 command/ indicate channel codes (c/i0) - overview . . . . . . . . . . . . 154 5.4 control procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.4.1 example of activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.4.2 activation initiated by the terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.4.3 activation initiated by the network termination nt . . . . . . . . . . . . . . . 157 5.5 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.5.1 iom-2 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.5.1.1 controller data access (cda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.5.2 idsl support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.5.2.1 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.5.2.2 s interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.5.3 serial data strobe signal and strobed data clock . . . . . . . . . . . . . . 174 psb 2154 table of contents page data sheet 2001-01-24 5.5.3.1 serial data strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.5.3.2 strobed iom-2 bit clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.5.4 iom-2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.5.4.1 handshake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.5.4.2 error treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.5.4.3 monitor channel programming as a master device . . . . . . . . . . 183 5.5.4.4 monitor time-out procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.5.4.5 monitor interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.5.5 c/i channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.5.6 d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.5.6.1 stop/go bit handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.5.6.2 tic bus d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . 188 5.5.6.3 s-bus priority mechanism for d-channel . . . . . . . . . . . . . . . . . . . . 190 5.5.6.4 state machine of the d-channel arbiter . . . . . . . . . . . . . . . . . . . . . 192 5.5.7 activation/deactivation of iom-2 interface . . . . . . . . . . . . . . . . . . . . . 194 5.6 hdlc controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 5.6.1 message transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.6.2 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.6.2.1 structure and control of the receive fifo . . . . . . . . . . . . . . . . . . . 199 5.6.2.2 receive frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 5.6.3 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 5.6.3.1 structure and control of the transmit fifo . . . . . . . . . . . . . . . . . . 208 5.6.3.2 transmit frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.6.4 access to iom-2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.6.5 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.6.6 hdlc controller interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.7 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 5.8 isdn register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.8.1 d-channel hdlc control and c/i registers . . . . . . . . . . . . . . . . . . . . 227 5.8.1.1 rfifod - receive fifo d-channel . . . . . . . . . . . . . . . . . . . . . . . 227 5.8.1.2 xfifod - transmit fifo d-channel . . . . . . . . . . . . . . . . . . . . . . . 227 5.8.1.3 istad - interrupt status register d-channel . . . . . . . . . . . . . . . . . 228 5.8.1.4 maskd - mask register d-channel . . . . . . . . . . . . . . . . . . . . . . . . 229 5.8.1.5 stard - status register d-channel . . . . . . . . . . . . . . . . . . . . . . . 230 5.8.1.6 cmdrd - command register d-channel . . . . . . . . . . . . . . . . . . . . 231 5.8.1.7 moded - mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.8.1.8 exmd1- extended mode register d-channel 1 . . . . . . . . . . . . . . . 234 5.8.1.9 timr2 - timer 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.8.1.10 sap1 - sapi1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8.1.11 sap2 - sapi2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8.1.12 rbcld - receive frame byte count low d-channel . . . . . . . . . . 237 5.8.1.13 rbchd - receive frame byte count high d-channel . . . . . . . . . 237 psb 2154 table of contents page data sheet 2001-01-24 5.8.1.14 tei1 - tei1 register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 5.8.1.15 tei2 - tei2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 5.8.1.16 rstad - receive status register d-channel . . . . . . . . . . . . . . . . 239 5.8.1.17 tmd -test mode register d-channel . . . . . . . . . . . . . . . . . . . . . . 240 5.8.1.18 cir0 - command/indication receive 0 . . . . . . . . . . . . . . . . . . . . . 241 5.8.1.19 cix0 - command/indication transmit 0 . . . . . . . . . . . . . . . . . . . . . 242 5.8.1.20 cir1 - command/indication receive 1 . . . . . . . . . . . . . . . . . . . . . 242 5.8.1.21 cix1 - command/indication transmit 1 . . . . . . . . . . . . . . . . . . . . . 243 5.8.2 transceiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 5.8.2.1 tr_conf0 - transceiver configuration register 0 . . . . . . . . . . . . 244 5.8.2.2 tr_conf1 - transceiver configuration register 1 . . . . . . . . . . . . 245 5.8.2.3 tr_conf2 - transmitter configuration register 2 . . . . . . . . . . . . 246 5.8.2.4 tr_sta - transceiver status register . . . . . . . . . . . . . . . . . . . . . 247 5.8.2.5 tr_cmd - transceiver command register . . . . . . . . . . . . . . . . . . 248 5.8.2.6 sqrr1 - s/q-channel receive register 1 . . . . . . . . . . . . . . . . . . 249 5.8.2.7 sqxr1- s/q-channel tx register 1 . . . . . . . . . . . . . . . . . . . . . . . 250 5.8.2.8 sqrr2 - s/q-channel receive register 2 . . . . . . . . . . . . . . . . . . . 250 5.8.2.9 sqrr3 - s/q-channel receive register 3 . . . . . . . . . . . . . . . . . . 251 5.8.2.10 istatr - interrupt status register transceiver . . . . . . . . . . . . . . . 251 5.8.2.11 masktr - mask transceiver interrupt . . . . . . . . . . . . . . . . . . . . . . 252 5.8.2.12 tr_mode - transceiver mode register 1 . . . . . . . . . . . . . . . . . . . 253 5.8.3 auxiliary interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 5.8.3.1 acfg1 - auxiliary configuration register 1 . . . . . . . . . . . . . . . . . . 254 5.8.3.2 acfg2 - auxiliary configuration register 2 . . . . . . . . . . . . . . . . . . 254 5.8.3.3 aoe - auxiliary output enable register . . . . . . . . . . . . . . . . . . . . . 256 5.8.3.4 arx - auxiliary interface receive register . . . . . . . . . . . . . . . . . . 256 5.8.3.5 atx - auxiliary interface transmit register . . . . . . . . . . . . . . . . . . 257 5.8.4 iom-2 and monitor handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 5.8.4.1 cdaxy - controller data access register xy . . . . . . . . . . . . . . . . . 257 5.8.4.2 xxx_tsdpxy - time slot and data port selection for chxy . . . . . 258 5.8.4.3 cdax_cr - control register controller data access ch1x . . . . . 260 5.8.4.4 tr_cr - control register transceiver data (iom_cr.ci_cs=0) . 261 5.8.4.5 trc_cr - control register transceiver c/i (iom_cr.ci_cs=1) . 262 5.8.4.6 bchx_cr - control register b-channel data . . . . . . . . . . . . . . . . 263 5.8.4.7 dci_cr - control register for d and ci1 data (iom_cr.ci_cs=0) 264 5.8.4.8 dcic_cr - control register for ci0 handler (iom_cr.ci_cs=1) . 265 5.8.4.9 mon_cr - control register monitor data . . . . . . . . . . . . . . . . . . . 266 5.8.4.10 sds_cr - control register serial data strobe . . . . . . . . . . . . . . . 267 5.8.4.11 iom_cr - control register iom data . . . . . . . . . . . . . . . . . . . . . . 268 5.8.4.12 sti - synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . . . . . 269 5.8.4.13 asti - acknowledge synchronous transfer interrupt . . . . . . . . . . 270 5.8.4.14 msti - mask synchronous transfer interrupt . . . . . . . . . . . . . . . . . 270 psb 2154 table of contents page data sheet 2001-01-24 5.8.4.15 sds_conf - configuration register for serial data strobes . . . . 271 5.8.4.16 mcda - monitoring cda bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 5.8.4.17 mor - monitor receive channel . . . . . . . . . . . . . . . . . . . . . . . . 272 5.8.4.18 mox - monitor transmit channel . . . . . . . . . . . . . . . . . . . . . . . 272 5.8.4.19 mosr - monitor interrupt status register . . . . . . . . . . . . . . . . . 273 5.8.4.20 mocr - monitor control register . . . . . . . . . . . . . . . . . . . . . . . 273 5.8.4.21 msta - monitor status register . . . . . . . . . . . . . . . . . . . . . . . . 274 5.8.4.22 mconf - monitor configuration register . . . . . . . . . . . . . . . . . 274 5.8.5 interrupt and general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 275 5.8.5.1 ista - interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 5.8.5.2 ista_init - interrupt status register initialize . . . . . . . . . . . . . . . . 276 5.8.5.3 auxi - auxiliary interrupt status register . . . . . . . . . . . . . . . . . . . . 276 5.8.5.4 auxm - auxiliary mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 5.8.5.5 mode1 - mode1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 5.8.5.6 id - identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 5.8.5.7 sres - software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . 280 5.8.5.8 timr3 - timer 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 5.8.6 b-channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 5.8.6.1 istab - interrupt status register b-channels . . . . . . . . . . . . . . . . 281 5.8.6.2 maskb - mask register b-channels . . . . . . . . . . . . . . . . . . . . . . . 282 5.8.6.3 starb - status register b-channels . . . . . . . . . . . . . . . . . . . . . . 283 5.8.6.4 cmdrb - command register b-channels . . . . . . . . . . . . . . . . . . . 284 5.8.6.5 modeb - mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 5.8.6.6 exmb - extended mode register b-channels . . . . . . . . . . . . . . . . 286 5.8.6.7 rah1 - rah1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 5.8.6.8 rah2 - rah2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 5.8.6.9 rbclb - receive frame byte count low b-channels . . . . . . . . . 288 5.8.6.10 rbchb - receive frame byte count high b-channels . . . . . . . . . 289 5.8.6.11 ral1 - ral1 register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 5.8.6.12 ral2 - ral2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 5.8.6.13 rstab - receive status register b-channels . . . . . . . . . . . . . . . 290 5.8.6.14 tmb -test mode register b-channels . . . . . . . . . . . . . . . . . . . . . . 291 5.8.6.15 rfifob - receive fifo b-channels . . . . . . . . . . . . . . . . . . . . . . 292 5.8.6.16 xfifob - transmit fifo b-channels . . . . . . . . . . . . . . . . . . . . . . 292 6 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 6.1 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 6.1.1 interrupt request / control flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 6.1.1.1 tcon - timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 6.1.1.2 eepint - eeprom interrupt control register . . . . . . . . . . . . . . . . 299 6.1.1.3 dirr - usb device interrupt request register . . . . . . . . . . . . . . . 299 6.1.1.4 dsir - device setup interrupt register . . . . . . . . . . . . . . . . . . . . . 301 6.1.1.5 epirn - endpoint interrupt request register . . . . . . . . . . . . . . . . . 301 psb 2154 table of contents page data sheet 2001-01-24 6.1.1.6 gepir - global endpoint interrupt request register . . . . . . . . . . . 303 6.1.1.7 ciari - configuration request interrupt register . . . . . . . . . . . . . 304 6.1.1.8 ista - isdn status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 6.1.2 interrupt enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 6.1.2.1 ien0 - interrupt enable register 0 . . . . . . . . . . . . . . . . . . . . . . . . . 306 6.1.2.2 ien1- interrupt enable register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 307 6.1.2.3 ien2 - interrupt enable register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 307 6.1.2.4 dier - usb device interrupt enable register . . . . . . . . . . . . . . . . 308 6.1.2.5 epien - usb endpoint interrupt enable register . . . . . . . . . . . . . . 309 6.1.2.6 epbcn - endpoint n buffer control register (n=0-7) . . . . . . . . . . . 310 6.1.2.7 ciarie - configuration request interrupt enable . . . . . . . . . . . . . 310 6.1.2.8 ista_init - isdn interrupt status register initialize . . . . . . . . . . . 311 6.1.3 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 6.1.3.1 ip0 / ip1 - endpoint priority registers . . . . . . . . . . . . . . . . . . . . . . 313 6.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 6.3 wakeup from suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 7 firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 7.1 firmware operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 7.2 boot loader firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 7.3 memory configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 7.3.1 firmware download mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 7.3.2 firmware execution in ram - single chip mode . . . . . . . . . . . . . . . . 324 7.3.3 firmware execution in ram - memory extension . . . . . . . . . . . . . . . 325 7.3.3.1 extension with shared memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 7.3.3.2 extension with separate memories . . . . . . . . . . . . . . . . . . . . . . . . 328 7.3.4 firmware execution in external eprom . . . . . . . . . . . . . . . . . . . . . . 329 7.4 usb models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 7.4.1 general usb model in siuc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 7.4.2 usb model in download mode (dfu) . . . . . . . . . . . . . . . . . . . . . . . . . 331 7.4.3 usb model in operational mode (cdc) . . . . . . . . . . . . . . . . . . . . . . . 331 7.4.4 usb configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 7.5 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 8 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 8.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 8.1.1 usb / microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 8.1.2 s-transceiver pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 8.1.2.1 receive pll (rpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 8.1.2.2 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 8.2 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 8.2.1 hardware reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 8.2.2 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 psb 2154 table of contents page data sheet 2001-01-24 8.3 auxiliary interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.3.1 mode dependent functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.3.2 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 8.3.2.1 direct microcontroller access to the eeprom . . . . . . . . . . . . . . . . 351 8.3.3 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.3.3.1 eepcmd - eeprom command register . . . . . . . . . . . . . . . . . . . 353 8.3.3.2 eepadr - eeprom byte address register . . . . . . . . . . . . . . . . . 354 8.3.3.3 eepdat - eeprom data register . . . . . . . . . . . . . . . . . . . . . . . . 354 8.3.3.4 eepsl - eeprom start / load register . . . . . . . . . . . . . . . . . . . . 355 8.4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 9 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 9.1 configuration of functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 9.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 9.2.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 9.2.2 suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 9.2.2.1 isdn module power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 9.3 sequence of operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 9.3.1 reset to active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 9.3.2 active to idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 9.3.3 idle to active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 9.3.4 active to suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 9.3.5 suspend to active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 9.3.6 interrupt wakeup control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 10.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 10.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 10.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 10.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 10.5 oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 10.6 recommended transformer specification . . . . . . . . . . . . . . . . . . . . . . . 375 10.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 10.8 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 10.9 memory interface timing - normal mode . . . . . . . . . . . . . . . . . . . . . . . . 379 10.10 memory interface timing - emulation mode . . . . . . . . . . . . . . . . . . . . . . 382 10.11 auxiliary interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 10.12 spi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 10.13 usb transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 10.14 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 11 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 psb 2154 list of figures page data sheet 2001-01-24 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2 isdn pc adapter for s interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3 isdn pc adapter for u and s interface. . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4 isdn voice/data terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5 isdn stand-alone terminal with pots interface . . . . . . . . . . . . . . . . 11 figure 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8 fetch execute sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9 c800 default memory map (firmware execution mode). . . . . . . . . . . 29 figure 10 external memory address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11 shared and separate external memory expansion. . . . . . . . . . . . . . . 41 figure 12 switching of read strobe signals for shared memory . . . . . . . . . . . . 41 figure 13 switching of read/write strobe signals for separate memory . . . . . . 42 figure 14 switching from download mode to operational mode. . . . . . . . . . . . . 44 figure 15 external program memory execution . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16 basic structure of a port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17 port alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 18 basic c800 mcu enhanced hooks concept configuration . . . . . . . . 49 figure 19 timer mode 0: 13-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 20 timer mode 1: 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 21 timer mode 2: 8-bit timer with auto-reload. . . . . . . . . . . . . . . . . . . . 54 figure 22 timer mode 3: two 8-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 23 external data memory access (onchip & offchip) via 8 data pointers . 61 figure 24 usb module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 25 memory buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 26 usb write access in single buffer mode - buffer handling . . . . . . . . 79 figure 27 single buffer mode : standard usb write access . . . . . . . . . . . . . . . 80 figure 28 usb read access in single buffer mode - buffer handling . . . . . . . . 81 figure 29 single buffer mode : standard usb read access . . . . . . . . . . . . . . . 82 figure 30 single buffer mode : usb read access with start-of-frame-done enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 31 usb read access in dual buffer mode - buffer handling. . . . . . . . . . 84 figure 32 usb write access in dual buffer mode - buffer handling. . . . . . . . . . 85 figure 33 dual buffer mode usb read access: buffer switching when maxlen is reached . . . . . . . . . . . . . . . . . . . . . 86 figure 34 dual buffer mode usb read access: buffer switching by setting bit done . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 35 dual buffer mode usb read access: buffer switching on sof with sofde=1. . . . . . . . . . . . . . . . . . . . . . . 88 figure 36 double buffer mode usb read access: data length greater than packet length (maxlen). . . . . . . . . . . . . . . 89 figure 37 endpoint buffer allocation (example: 7+1 endpoints) . . . . . . . . . . . . . 92 psb 2154 list of figures page data sheet 2001-01-24 figure 38 usb memory address generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 39 usb onchip driver circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 40 full speed usb driver signal waveforms. . . . . . . . . . . . . . . . . . . . . 101 figure 41 high speed device cable and resistor connection . . . . . . . . . . . . . 101 figure 42 device attached - device detached detection in self-powered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 43 usb register set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 44 usb interface get_status registers . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 45 functional block diagram of the siuc-x. . . . . . . . . . . . . . . . . . . . . . 125 figure 46 timer 1 and 2 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . 126 figure 47 timer 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 48 timer 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 49 acl indication of activated layer 1. . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 50 acl configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 51 wiring configurations in user premises . . . . . . . . . . . . . . . . . . . . . . 130 figure 52 s/t -interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 53 frame structure at reference points s and t (itu i.430). . . . . . . . . 132 figure 54 multiframe synchronization using the m-bit. . . . . . . . . . . . . . . . . . . . 135 figure 55 frame relationship in te mode (m-bit output) . . . . . . . . . . . . . . . . . 135 figure 56 data delay between iom-2 and s/t interface (te mode) . . . . . . . . . 136 figure 57 data delay between iom-2 and s/t interface with s/g bit evaluation (te mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 58 equivalent internal circuit of the transmitter stage . . . . . . . . . . . . . 138 figure 59 equivalent internal circuit of the receiver stage . . . . . . . . . . . . . . . 139 figure 60 connection of line transformers and power supply to the siuc-x . 140 figure 61 external circuitry for transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 62 external circuitry for symmetrical receivers. . . . . . . . . . . . . . . . . . . 141 figure 63 disabling of s/t transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 64 external loop at the s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 65 layer-1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 66 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 67 state transition diagram (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 68 state transition diagram of unconditional transitions (te) . . . . . . . 149 figure 69 example of activation/deactivation initiated by the terminal . . . . . . 155 figure 70 example of activation/deactivation initiated by the terminal (te). activation/deactivation completely under software control . . . . . . . 156 figure 71 example of activation/deactivation initiated by the network termination (nt). activation/deactivation completely under software control . . . . . . . 157 figure 72 iom-2 frame structure in terminal mode . . . . . . . . . . . . . . . . . . . . . 159 figure 73 architecture of the iom handler (example configuration). . . . . . . . . 161 figure 74 data access via cdax1 and cdax2 register pairs . . . . . . . . . . . . . . 163 psb 2154 list of figures page data sheet 2001-01-24 figure 75 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) shifting and looping data 164 figure 76 data access when looping tsa from du to dd . . . . . . . . . . . . . . . . 165 figure 77 data access when shifting tsa to tsb on du (dd) . . . . . . . . . . . . . 166 figure 78 example for monitoring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 79 interrupt structure of the synchronous data transfer . . . . . . . . . . . . 169 figure 80 examples for the synchronous transfer interrupt control with one enabled stixy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 81 timeslot assignment on iom-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 82 examples for hdlc controller access . . . . . . . . . . . . . . . . . . . . . . . 172 figure 83 timeslot assignment on s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 84 mapping of bits from iom-2 to s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 85 data strobe signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 86 strobed iom-2 bit clock. register sds_conf programmed to 01 h 176 figure 87 examples of monitor channel applications in iom-2 te mode . . 177 figure 88 monitor channel protocol (iom-2) . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 89 monitor channel, transmission abort requested by the receiver. . . 182 figure 90 monitor channel, transmission abort requested by the transmitter. 182 figure 91 monitor channel, normal end of transmission . . . . . . . . . . . . . . . . . 183 figure 92 monitor interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 93 cic interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 94 structure of last octet of ch2 on dd . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 95 applications of tic bus in iom-2 bus configuration . . . . . . . . . . . . . 188 figure 96 structure of last octet of ch2 on du . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 97 d-channel access control on the s-interface . . . . . . . . . . . . . . . . . . 191 figure 98 state machine of the d-channel arbiter (simplified view). . . . . . . . . 192 figure 99 deactivation of the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 100 activation of the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 101 rfifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 102 data reception procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 103 reception sequence example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 104 receive data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 105 data transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 106 transmission sequence example . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 107 transmit data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 108 interrupt status registers of the hdlc controllers . . . . . . . . . . . . . . 215 figure 109 layer 2 test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 110 register mapping of the siuc-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 111 interrupt request sources (part 1) - miscellaneous interrupts . . . . . 293 figure 112 interrupt request sources (part 2) - usb endpoint interrupts . . . . . 294 psb 2154 list of figures page data sheet 2001-01-24 figure 113 interrupt request sources (part 3) - usb device interrupts . . . . . . . 295 figure 114 interrupt request sources (part 4) - isdn interrupts . . . . . . . . . . . . 296 figure 115 isdn interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 figure 116 wakeup sources in suspend mode. . . . . . . . . . . . . . . . . . . . . . . . . . 315 figure 117 bootmode procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 figure 118 shared and separate external memory expansion. . . . . . . . . . . . . . 322 figure 119 memory map for firmware download . . . . . . . . . . . . . . . . . . . . . . . . 323 figure 120 firmware execution in ram - single chip mode . . . . . . . . . . . . . . . . 324 figure 121 shared memory expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 figure 122 firmware execution in ram - example with one 32k memory. . . . . 326 figure 123 firmware execution in ram - example with one 64k memory. . . . . 327 figure 124 firmware execution in ram - example with separate memories . . . 328 figure 125 memory map for firmware execution in external eprom . . . . . . . . 329 figure 126 general usb model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 figure 127 usb configuration in dfu mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 figure 128 siuc-x firmware operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 figure 129 usb configuration in cdc mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 figure 130 siuc clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 figure 131 phase relationships of siuc-x clock signals . . . . . . . . . . . . . . . . . 343 figure 132 reset generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 figure 133 spi read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 figure 134 spi write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 figure 135 external circuitry of the voltage regulator . . . . . . . . . . . . . . . . . . . . 356 figure 136 clocks in suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 figure 137 voltage regulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 figure 138 oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 figure 139 input/output waveform for ac tests. . . . . . . . . . . . . . . . . . . . . . . . . 376 figure 140 iom? timing (te mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 figure 141 definition of clock period and width . . . . . . . . . . . . . . . . . . . . . . . . . 378 figure 142 program memory read cycle - normal mode . . . . . . . . . . . . . . . . . . 379 figure 143 data memory read cycle - normal mode . . . . . . . . . . . . . . . . . . . . . 380 figure 144 data memory write cycle - normal mode . . . . . . . . . . . . . . . . . . . . . 381 figure 145 program memory read cycle - emulation mode. . . . . . . . . . . . . . . . 382 figure 146 data memory read cycle - emulation mode. . . . . . . . . . . . . . . . . . . 383 figure 147 data memory write cycle - emulation mode . . . . . . . . . . . . . . . . . . . 384 figure 148 aux interface i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 figure 149 aux interface i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 figure 150 load for d+/d- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 figure 151 differential input sensitivity range . . . . . . . . . . . . . . . . . . . . . . . . . . 389 figure 152 reset signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 psb 2154 list of tables page data sheet 2001-01-24 table 1 pin definition - iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 pin definition - auxiliary interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 pin definition - external memory interface . . . . . . . . . . . . . . . . . . . . . 18 table 4 pin definition - miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5 pin definition - power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6 pin definition - iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7 pin definition - auxiliary interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8 pin definition - external memory interface . . . . . . . . . . . . . . . . . . . . . 24 table 9 pin definition - miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10 mapping of internal and external addresses . . . . . . . . . . . . . . . . . . . . 30 table 11 special function registers - functional blocks. . . . . . . . . . . . . . . . . . 33 table 12 special function registers - numerically ordered addresses . . . . . . . 37 table 13 usb device and endpoint registers . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14 alternate functions of port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 15 usb transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 16 buffer length and base address values . . . . . . . . . . . . . . . . . . . . . . . 91 table 17 usb configuration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 18 bitfield definition of usb configuration block . . . . . . . . . . . . . . . . . . . 95 table 19 standard device requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 20 siuc-x timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 21 s/q-bit position identification and multiframe structure . . . . . . . . . . 133 table 22 examples for synchronous transfer interrupts . . . . . . . . . . . . . . . . . 169 table 23 transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 24 receive direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 25 hdlc controller address range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 26 receive byte count with rbc11...0 in the rbchx/rbclx registers 200 table 27 receive information at rme interrupt . . . . . . . . . . . . . . . . . . . . . . . . 207 table 28 xpr interrupt (availability of xfifox) after xtf, xme commands. . 209 table 29 interrupt priority order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 table 30 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 table 31 enabling / disabling of wakeup sources. . . . . . . . . . . . . . . . . . . . . . 316 table 32 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 table 33 siuc configuration data for usb descriptors. . . . . . . . . . . . . . . . . . 334 table 34 organisation of eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 35 usb power consumption limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 table 36 iom clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 37 reset source selection (mode1.rss2,1) . . . . . . . . . . . . . . . . . . . . 346 table 38 aux pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 psb 2154 data sheet 1 2001-01-24 preface the single chip isdn usb controller (siuc-x) is an optimized low cost solution for host based connectivity to isdn through usb. this document provides reference information on the features and possible applications. organization of this document this data sheet is divided into 11 chapters. it is organized as follows: chapter 1, overview gives a general description of the product, lists the key features, describes functional modules and presents some typical applications. chapter 2, pin description lists pins with associated signals, categorizes signals according to function, and describes signals. chapter 3, c800 microcontroller describes the embedded c800 8-bit microcontroller, memory organisation, external bus interface, special function registers and emulation concept. chapter 4, usb module covers the usb implementation on the siuc describing the transfer modes, the memory buffer operation, the usb device framework and the usb registers. chapter 5, isdn module includes all the modules, modes and interfaces related to isdn, especially the iom-2 interface, the s-transceiver and the hdlc controllers. chapter 6, interrupt system describes the microcontroller interrupt sources along with all interrupt status and interrupt enable registers, and describes interrupt priority handling. chapter 7, firmware lists the different ways of running firmware, along with the memory map for commonly used configurations, and describes the different usb models used with the siuc. chapter 8, general features includes the clock and reset generation within the device, the auxiliary and spi interfaces, and the voltage regulator. chapter 9, operational description briefly elaborates the operational modes like active, idle, suspend etc. within the device along with the programming sequence to be followed in different modes. chapter 10, electrical characteristics chapter 11, package outlines psb 2154 data sheet 2 2001-01-24 related documents usb specification v1.1, september 23, 1998 usb class definitions for communication devices (cdc) v1.1, january 19, 1999 usb device class specification for device firmware upgrade (dfu) v1.0, may 13, 1999 isdn pc adapter circuit (ipac-x) psb 21150, version 1.1, preliminary data sheet, 12.99 c540u / c541u 8-bit cmos microcontroller, user?s manual 11.97. c501 8-bit single-chip microcontroller, user?s manual 04.97 embedded c165 with usb, isdn terminal adapter and hdlc, utah, data sheet. psb 2154 overview data sheet 3 2001-01-24 1overview the single chip isdn usb controller (siuc-x) integrates all necessary functions on a single chip for a host based isdn s-interface access solution through usb. it combines the features of the isdn pc adapter circuit (ipac psb 2115) and the c541u 8-bit siemens microcontroller with usb. on the isdn side, it includes the s-transceiver (layer 1), an hdlc controller for the d- channel and two protocol controllers for each b-channel. they can be used for hdlc protocol or transparent access. the fifo size of the b-channel buffers is 128 bytes per channel and per direction. on the usb side, it includes a full speed usb transceiver, supports bus powered operation and is compliant with usb specification v1.1 and the communication device class (cdc) specification v1.1 for isdn devices. the endpoints can be controlled by the microcontroller by special function registers. a boot loader in rom allows firmware download to internal and external memory via usb according to the usb device class specification for device firmware upgrade (dfu) v1.0. the embedded new c800 microcontroller core (8-bit) enables transparent or hdlc- framed exchange of b-channel data between the s-interface and usb. in addition, it provides lower level d-channel access control functions. firmware can be developed using external flash/rom. emulation is supported through enhanced hooks technology tm . 3 sets of c ports are available for optionally connecting external memory. in applications not requiring external memory, they can be used as general purpose i/os. additionally, an 8 line auxiliary i/o interface has been built in. these programmable i/o lines may be used to connect other peripheral components to the siuc-x, which need software control or have to forward status information to the c. the spi interface for serial eeprom communication is also multiplexed on to these lines. 3 programmable led output ports are available, one of them can indicate the activation status of the s- interface automatically. the onchip voltage regulator supports the design of bus powered applications. the siuc-x is produced in advanced cmos technology. data sheet 4 2001-01-24 type package psb 2154 p-mqfp-80-1 single chip isdn usb controller siuc-x psb 2154 version 1.3 p-mqfp-80-1 1.1 features general single chip host based isdn solution for usb 3.3v power supply programmable reset sources onchip pll for 48 mhz clock generation 5v tolerant i/os onchip voltage regulator for bus-powered operation (patent pending) isdn (s-interface, 2b+d channels) s/t-transceiver (itu-t i.430) operating in te mode d-channel and b-channel protocol controllers (hdlc) different types of protocol support depending on operating mode (non-auto mode, transparent mode 1-3, extended transparent mode) iom-2 interface, single/double clock with strobe signals monitor and c/i-channel protocol to control peripheral devices 128 byte fifo buffers with programmable fifo thresholds per b-channel per direction 64 byte fifo buffers per direction with programmable fifo thresholds for d-channel d-channel access mechanism transformer ratio 1:1 2 timers programmable between 1 ms to 14.336 s. psb 2154 overview data sheet 5 2001-01-24 microcontroller & peripherals 8-bit c800 cpu, full software/toolset compatible to standard 80c51/80c52 microcontrollers 48 mhz operating frequency, equivalent to 4 mips 4 kbyte onchip standard rom program memory (boot loader), up to 64 kbyte external program memory for firmware development 256 byte onchip data ram 16 kbyte onchip ram (xram) flexibly programmable as program and/or data space external memory extention up to 64 kbyte program and 62 kbyte data memory ports 0, 2 and 3 can be used as general purpose i/os or as memory interface two lines can be used as external interrupt source, one of them can indicate the usb device attached status in self powered mode demultiplexed address/data bus allows glueless interfacing of external memory optimized layout for external memory connection 14 interrupt sources to cpu (1 external, 13 internal with 2 usb, 1 spi and 8 isdn interrupts) selectable at 4 priority levels 8 data pointers two 16-bit timers: timer 0 and timer 1 onchip emulation support logic using enhanced hooks technology tm usb compliant to - usb specification v1.1 - usb communication device class (cdc) specification v1.1 - usb device firmware upgrade (dfu) specification v1.0 onchip usb transceiver 12 mbit/s full speed operation 7 software configurable endpoints, in addition to the bi-directional control endpoint 0 fw supports 2 configurations by default: usb device firmware upgrade (dfu) usb communication device class (cdc) dfu configuration with 1 interface and 1 endpoint (ep0) cdc configuration with 4 additional interfaces and 2 alternate settings each, supporting 8 endpoints (ep0 - ep7) all usb transfer modes supported (bulk, isochronous, interrupt and control) bus-powered operation possible (no external power supply necessary) low power device, <100ma (operational), <500 a (suspend) optional loading of customized configuration data (e.g. vendor id, product id, ... ) from external eeprom psb 2154 overview data sheet 6 2001-01-24 firmware siuc-x comes along with firmware and drivers fully supporting isdn data access according to usb cdc v1.1 onchip bootloader supports dfu class: firmware can easily be downloaded via usb to internal memory (flexibility for firmware upgrades) customer can develop own firmware using internal/external memory miscellaneous 8 line programmable auxiliary i/o interface with interrupt inputs spi interface for optional connection to an external eeprom 3 led output ports (one is capable to indicate s-bus activation status automatically) strap pins for identification of different hw configurations psb 2154 overview data sheet 7 2001-01-24 1.2 logic symbol the logic symbol shows all functions of the siuc-x. it must be noted, that not all functions are available simultaneously, but depend on the selected mode. pins which are marked with a ? * ? are multiplexed and not available in all modes. figure 1 logic symbol port 0 (data) 8 port 2 (msb address) ad0-7 (lsb address) port 3 (dadd, int0, wr, rd, pwr) ale / cs psen ea reset mmod bmod 2 d+ d- 8 8 5 usb interface vdd vdda vddap vddu +3.3v 0v 7.68 mhz 100 ppm vss vssa vssap vssu vssar vreg1 vreg2 voltage regulator sr1 sr2 sx1 sx2 s interface du dd fsc dcl bcl sds / rsto iom-2 interface aux0-7* 8 sdi* sdo* sck* scs* eld* spi interface * auxiliary interface* eaw external awake xtal1 xtal2 svn0/1 * system version number * memory interface 2154_11x int1/2* 2 external interrupts* aux6/7* acl 3 led output* mbit * multiframe sync. test 0v psb 2154 overview data sheet 8 2001-01-24 1.3 typical applications the siuc-x is suited for usb host based applications. the s interface is a 4-line 192 kbit/s interface while the 2-line usb interface works at 12 mhz. figure 2 to figure 5 give a general overview of system integration with siuc-x. isdn pc adapter for s interface an isdn adapter for a pc is built around the siuc-x using the usb interface ( figure 2 ). the onchip voltage regulator allows bus powered operation without the necessity of an external regulator. 3 led ports can indicate different status information to the user. this single chip solution enables design of an embedded device cable linking usb to isdn ("cable with a bump"). the siuc-x also enables an optimized layout and glueless connection of external memory, to provide a small form factor even in non single chip applications. figure 2 isdn pc adapter for s interface siuc-x psb 2154 flash / ram (optional) 2 1 5 4 _ 1 2 . v s d usb host interface s interface nt usb s pc adapter psb 2154 overview data sheet 9 2001-01-24 isdn pc adapter for u and s interface a dual mode isdn adapter which supports u and s interface may be realized using the siuc-x together with the u transceiver psb 21911 iec-q te ( figure 3 ). as a dual mode adapter it can be connected to the s interface of an nt (e.g. in europe) whereby the u transceiver is disabled, or it is connected directly to the u interface (e.g. in north america) while the s transceiver of the siuc-x is unused. figure 3 isdn pc adapter for u and s interface 2154_13.vsd siuc-x psb 2154 flash / ram (optional) usb host interface s interface s u co iec-q te psb 21911 u interface s u co nt usb pc adapter usb pc adapter psb 2154 overview data sheet 10 2001-01-24 isdn voice/data terminal figure 4 shows a voice data terminal where the siuc-x provides its functionality as data controller and s interface whithin a two chip solution. during isdn calls the arcofi-sp psb 2163 provides speakerphone functions and includes a dtmf generator. additionally, a dtmf receiver or keypad may be connected to the auxiliary interface of the siuc-x. the isdn features of this phone are controlled by the pc and while the host is switched off basic phone call functionality is provided. figure 4 isdn voice/data terminal siuc-x psb 2154 flash / ram (optional) usb host interface s interface arcofi-sp psb 2163 nt 2154_14a dtmf rx or keypad usb s psb 2154 overview data sheet 11 2001-01-24 isdn terminal adapter with usb data port the siuc-x can be used as a microcontroller based terminal adapter ( figure 5 ) that is connected to the communications interface of a pc. connection of analog terminals (e.g. telephone or fax) is enabled by the duslic chipset with its dual channel pots interface. leds for status information and general purpose input/output control functions can directly be handled by the siuc-x. figure 5 isdn stand-alone terminal with pots interface duslic 2154_14b.vsd siuc-x psb 2154 flash / ram (optional) usb host interface s interface nt slicofi2 peb 3265 slic-x peb 4265 slic-x peb 4265 2xtip/ring ta status leds usb s t/r t/r psb 2154 overview data sheet 12 2001-01-24 1.4 functional description the data transfer from usb to s-interface and vice versa takes place through the c xram and a set of fifos for each channel. the c ports enable the connection of external memory and provide emulation support. the auxiliary interface serves as a general purpose i/o in addition to providing external interrupt sources and lines for the spi interface. all registers corresponding to different peripherals are available in the special function register (sfr) map of the c. the isdn specific registers are located in the external memory map of the c. 1.4.1 functional block diagram figure 6 gives an overview of the functional blocks. figure 6 block diagram port 0 c800 cpu usb on chip emulation support module 16384 x 8 xram 4096 x 8 rom 256 x 8 iram port 2 port 3 address bus auxiliary interface i/o spi eeprom general purpose i/o usb interface (data) fifo fifo fifo b-channel hdlc b-channel hdlc d-channel hdlc monitor c/i-channel tic-bus iom-2 handler iom-2 interface isdn basic access osc dpll iom-2 s interface memory interface, emulation 2154_10a voltage regulator usb interface (power) psb 2154 pin description data sheet 13 2001-01-24 2 pin description 2.1 pin diagram figure 7 pin diagram sr2 siuc-x psb 2154 12345 6 7 8 910111213141516 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 38 39 40 35 36 37 32 33 34 29 30 31 26 27 28 23 24 25 21 22 63 62 61 66 65 64 69 68 67 72 71 70 75 74 73 78 77 76 80 79 sr1 vdda vssa sx2 sx1 vssap vddap xtal2 xtal1 reset acl test vdd vss bmod0 p0.0/ad0 vdd vss p2.3/a11 a3 a4 vss vddu d+ d- vssu aux7 p3.0/dadd p3.1/int0 p3.3/rd vdd vss bcl du dd fsc dcl res_l eaw sds/rsto vdd vss aux0 aux1 aux2 aux3 aux4 aux5 aux6 vssar vreg1 vreg2 2154_15x.vsd a0 a1 a2 bmod1 a5 a6 p2.1/a9 p2.0/a8 p2.5/a13 p3.2/wr p3.4/pwr a7 p2.7/a15 p2.6/a14 p2.4/a12 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ale / cs p2.2/a10 ea psen mmod psb 2154 pin description data sheet 14 2001-01-24 2.2 pin definition table 1 pin definition - iom-2 interface pin no. symbol input (i) output (o) function 64 fsc o frame sync 8-khz frame synchronisation signal. the rising edge indicates the beginning of the iom frame (high during channel 0). 65 dcl o data clock iom clock signal of twice the iom data rate (1.536 mhz). the first rising edge is used to transmit data, the second falling edge is used to sample data. 62 du i data upstream iom data signal in upstream direction. 63 dd o(od) data downstream iom data signal in downstream direction. 61 bcl o bit clock bit clock output, identical to iom data rate , derived from the dcl output clock (bcl = dcl/2 = 768 khz). 68 sds / rsto o (od) serial data strobe / reset output programmable strobe signal (push pull characteristic) for time slot and/or d-channel indication on iom-2. it can optionally be used as reset output (open drain characteristic). psb 2154 pin description data sheet 15 2001-01-24 table 2 pin definition - auxiliary interface pin no. symbol input (i) output (o) function 71 72 73 aux0 aux1 aux2 i/o auxiliary port 0 - 2 - general input/output ports these pins are individually programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. 74 aux3 i/o auxiliary port 3 non spi mode: aux3 (input/output) if not used for the spi interface, this pin is programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. spi mode: eld (input, during reset) - eeprom load this pin is strapped high during reset to indicate the c that an eeprom is connected (e.g. for loading usb id values). spi mode: scs (output, after reset) serial chip select to eeprom. this pin has an internal pulldown resistor, i.e. for the eld function an external pullup resistor must be connected to indicate that an eeprom is connected. 75 aux4 i/o auxiliary port 4 non spi mode: aux4 (input/output) if not used for the spi interface, this pin is programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. spi mode: sdi (input) serial data input on the spi interface to be connected to the so pin of the eeprom. all modes: svn0 - system version number 0 (input) during reset the state of this pin (pull up/down resistor) is latched to the internal system version number register. after reset this pin performs the functions described above. an internal pull down resistor is provided. mbit - multiframe synchronization (output) if selected via acfg2.a4sel=1 the pin aux4 is used for multiframe synchronization, i.e. it is an m-bit output. psb 2154 pin description data sheet 16 2001-01-24 76 aux5 i/o auxiliary port 5 non spi mode: aux5 (input/output) if not used for the spi interface, this pin is programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. spi mode: sdo (output) serial data output on the spi interface to be connected to the si pin of the eeprom. all modes: svn1 - system version number 1 (input) during reset the state of this pin (pull up/down resistor) is latched to the internal system version number register. after reset this pin performs the functions described above. an internal pull down resistor is provided. table 2 pin definition - auxiliary interface (cont ? d) pin no. symbol input (i) output (o) function psb 2154 pin description data sheet 17 2001-01-24 77 aux6 i/o auxiliary port 6 non spi mode: aux6 (input/output), int1 if not used for the spi interface, this pin is programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. in addition to that, as an input, it can generate an interrupt (auxi.int1) which is maskable in auxm. int1. the interrupt input is either edge or level triggered (acfg2.el1). as an output it is able to sink higher current and so allows for direct connection of an led in stand-alone applications. an internal pullup resistor is connected to this pin. spi mode: sck (output) serial clock output to eeprom 5 aux7 i/o auxiliary port 7 aux7 (input/output), int2 this pin is programmable as general input/output. the state of the pin can be read from (input) / written to (output) a register. in addition to that, as an input, it can generate an interrupt (auxi.int2) which is maskable in auxm. int2. the interrupt input is either edge or level triggered (acfg2.el2). as an output it is able to sink higher current and so allows for direct connection of an led in stand-alone applications. an internal pullup resistor is connected to this pin. sgo instead of the above described function, aux7 can also be programmed to output the s/g bit signal from the iom- 2 dd line. table 2 pin definition - auxiliary interface (cont ? d) pin no. symbol input (i) output (o) function psb 2154 pin description data sheet 18 2001-01-24 table 3 pin definition - external memory interface pin no. symbol input (i) output (o) function 41 mmod i memory mode select for memory extension mmod is used to indicate to the c whether program and data share the same external memory device ( ? 0 ? ) or physically separate memories for program and data are connected ( ? 1 ? ). this pin has no effect on the hardware functions of the device. 9 psen o program store enable this control signal enables the external program memory to the bus during external fetch operations. it is activated every six 48 mhz clock periods except during external data memory accesses. the signal remains high during internal program execution. 11 ale /cs i/o address latch enable / chip select - normal mode: this pin is used as low active chip select signal to external program and data memory. - emulation mode: during reset this pin is used as an input to enter emulation mode ( ? 0 ? ). an internal pull-up resistor is provided. in emulation mode this output is used for latching the address into external memory during normal operation. it is activated every 6 48mhz clock periods except during an external data memory access. 8ea i/o external access enable when held high, the c800 executes instructions from the internal program memory till internal program space is exceeded. when held low, the c800 fetches all instructions from the external program memory. it is used as an output during emulation. 23 22 21 40 39 38 37 36 a.0-a.7 o address port this is an 8-bit output port which is used to emit the low- order address byte for access to external program memory. psb 2154 pin description data sheet 19 2001-01-24 24 20 19 18 17 16 15 12 p0.0 - p0.7 i/o port 0 this is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1 ? s written to them float, and in that state can be used as high-impedance inputs. port 0 is also the data bus during accesses to external program and data memory. in this application it uses strong internal pullup resistors when issuing 1 ? s. for emulation port 0 is used as the multiplexed low-order address bus and data bus. 29 28 10 26 35 30 34 33 p2.0 - p2.7 i/o port 2 this is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have 1 ? s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @ dptr). in this application it uses strong internal pullup resistors when issuing 1 ? s. during accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 issues the contents of the xpage register. p3.0 - p3.4 i/o port 3 this is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 3 pins that have 1 ? s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current because of the internal pullup resistors. port 3 also contains the interrupt, usb attach/detach status and external memory strobe pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a 1 for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: table 3 pin definition - external memory interface (cont ? d) pin no. symbol input (i) output (o) function psb 2154 pin description data sheet 20 2001-01-24 6 7 31 25 32 i i o o o p3.0 / dadd device attached input p3.1 / int0 external interrupt 0 input p3.2 / wr write control output latches the data byte from port 0 into the external data memory. p3.3 / rd read control output enables the output of the external data memory. p3.4 / pwr program write signal this signal is used as write signal to external program memory during firmware download operation. the port names port 0, port 2 and port 3 have been intentionally selected for compliance with the c5xx c series. port 1 is not implemented in the siuc-x. table 4 pin definition - miscellaneous pin no. symbol input (i) output (o) function 2d+ i/o usb d+ data line the pin d+ can directly be connected to the usb cable (transceiver is integrated onchip). a pull up resistor (1.5k 5%) must be connected to d+ to select full speed operation according to the usb spec. 3d- i/o usb d- data line the pin d- can directly be connected to the usb cable. (transceiver is integrated onchip). 48 reset i reset a low on this input forces the siuc-x into a reset state. the duration of this pulse must be at least 4 ms to stabilize the internal oscillator. following the reset, the microcontroller executes a complete machine cycle to initialize indirectly resetable registers. 43 42 bmod0 bmod1 i boot mode select 1,0 selects the mode for firmware operation. pin ea determines if the firmware should start from external offchip memory. table 3 pin definition - external memory interface (cont ? d) pin no. symbol input (i) output (o) function psb 2154 pin description data sheet 21 2001-01-24 67 eaw i external awake if a negative level on this input is detected, the siuc-x generates an interrupt (auxi.eaw), and if enabled, a reset pulse. 47 acl o activation led this pin can either function as a programmable output or automatically indicate the activated state of the s interface by a logic 0. an led with pre-resistance may directly be connected to acl . 55 56 sx1 sx2 o o s-bus transmitter output differential output for the s-transmitter. positive negative 59 60 sr1 sr2 i i s-bus receiver input differential inputs for the s-receiver. 51 xtal1 i oscillator input input pin of oscillator or input from external clock source. 7.68 mhz crystal or clock required. 52 xtal2 o oscillator output output pin of oscillator. not connected if external clock source is used. 46 test i test this pin is reserved for test purposes during manufacturing and should be connected to gnd. 66 res_l i reserved, pull low this pin is reserved and must be connected to vss. table 5 pin definition - power supply pin no. symbol input (i) output (o) function 13 45 50 69 vdd i digital supply voltage, +3.3v for core logic and oscillator 58 vdda i analog supply voltage, +3.3v for s-transceiver table 4 pin definition - miscellaneous (cont ? d) pin no. symbol input (i) output (o) function psb 2154 pin description data sheet 22 2001-01-24 note: some of the pins are used to latch certain values during reset. these are ale/cs , aux3/eld, aux4/svn0 and aux5/svn1. the values on these pins must be held stable for at least 600 ns after reset. 53 vddap i analog supply voltage, +3.3v for pll 1 vddu i analog supply voltage, +3.3v for usb module 14 27 44 49 70 vss i digital gnd, for core logic and oscillator 57 vssa i analog gnd, for s-transceiver 54 vssap i analog gnd, for pll 4vssu i analog gnd, for usb module 79 80 vreg1 vreg2 voltage regulator these two pins from the internal voltage regulator are used to connect some additional external components for regulation. the regulator uses the usb power supply (bus-powered mode) to generate the +3.3v supply for the siuc-x which must externally be connected to the vddx pins (the supply is not connected internally). if the voltage regulator is not used (e.g. usb self-powered mode) vreg1/2 are left not connected and the external power supply is connected to the vddx pins. a detailed description and circuitry can be found in chapter 8.4 and chapter 10.3 . 78 vssar i analog gnd, for voltage regulator table 5 pin definition - power supply (cont ? d) pin no. symbol input (i) output (o) function psb 2154 pin description data sheet 23 2001-01-24 2.3 pin states in operating modes the following table provides an overview on the behaviour of the pins and ports in the different operating modes. in normal operating mode most of the pins can be used in different ways therefore the behaviour in operational mode is not listed. the following abbreviations are used: i input pin this pin needs to be terminated externally if no internal pull up/down resistor is available or if the internal resistor is switched off, to avoid malfunctions due to floating input. o output pin this pin keeps the level ( ? 0 ? or ? 1 ? ) which was driven just before suspend mode was entered. z high impedant this pin is an output pin but the output driver is switched off (floating), therefore this pin does not need to be terminated but can be left open. note: "pull up" at any place in the tables below refers to internal pull up resistors only and not to any external resistors. internal resistors are switched off in suspend and idle mode to avoid an increased leakage current. some pins can show different characteristic depending on the mode which was used before suspend mode was entered. table 6 pin definition - iom-2 interface pin no. symbol during reset in suspend mode in idle mode comment 64 fsc o o or i o or i note 1 65 dcl o o or i o or i 62 du z o or i o or i note 2 63 dd z o or i o or i 61 bcl o o o 68 sds / rsto o z or o z or o note 7 psb 2154 pin description data sheet 24 2001-01-24 table 7 pin definition - auxiliary interface pin no. symbol during reset in suspend mode in idle mode comment 71 72 73 aux0 aux1 aux2 i i i i or o i or o i or o i or o i or o i or o note 3 74 aux3 i i or o i or o 75 aux4 i i or o i or o 76 aux5 i i or o i or o 77 aux6 i (with pull up) i or o (w/o pull up) i or o (w/o pull up) 5aux7 i (with pull up) i or o (w/o pull up) i or o (w/o pull up) table 8 pin definition - external memory interface pin no. symbol during reset in suspend mode in idle mode comment 41 mmod i i i 9 psen ooo 11 ale /cs i (with pull up) o (w/o pull up) o (w/o pull up) note 4 8ea i i i note 5 23 22 21 40 39 38 37 36 a.0 - a.7 o o o 24 20 19 18 17 16 15 12 p0.0 - p0.7 z o or z o or z note 6 psb 2154 pin description data sheet 25 2001-01-24 29 28 10 26 35 30 34 33 p2.0 - p2.7 o o o p3.0 - p3.4 6 7 31 25 32 dadd int0 wr rd pwr i i (with pull up) o o o o or i o or i (w/o pull up) o or z o or z o or z o or i o or i (w/o pull up) o or z o or z o or z note 6 table 9 pin definition - miscellaneous pin no. symbol during reset in suspend mode in idle mode 2d+ iii 3d- iii 48 reset i (with pull up) i (w/o pull up) i (with pull up) 43 42 bmod0 bmod1 i i i i i i 67 eaw iii 47 acl ooo 55 56 sx1 sx2 z z z z z z 59 60 sr1 sr2 i i i i i i table 8 pin definition - external memory interface (cont ? d) pin no. symbol during reset in suspend mode in idle mode comment psb 2154 pin description data sheet 26 2001-01-24 note: 1) in normal mode (i.e. the transceiver is not switched off) fsc and dcl become output in suspend/idle mode. however, if the remote wakeup feature from the s transceiver should be disabled, the transceiver must be switched off (tr_conf0.dis_tr = 1) which has the effect that fsc and dcl become input and therefore must be terminated externally (pull up resistors). 2) if du and dd are programmed to open drain characteristic (default mode) they become input ports during suspend/idle mode. if they are programmed to push pull drivers (iom_cr.dis_od=1), they become output and so no terminating resistor is required. 3) all pins from the auxiliary port keep their selected direction (input or ouput) and their programmed level as outputs (?0? or ?1?) when going to suspend/idle mode. 4) during reset a low level on pin ale/cs selects the enhanced hooks emulation mode, but due to the internal pull up resistor this pin can be left open on the system board. 5) this pin is directly connected to vdd or vss on the system board. 6) port 0 and port 3 have the same characteristics. in single chip mode these ports may not be used, therefore they should be switched as output by writing ?0? to them, and so external terminating resistors are not necessary. if external memory is used these ports (except dadd and int0 ) are switched as output with disabled output drivers (floating). if any of these pins (including dadd and int0 ) is programmed as input they must be terminated externally. 7) the behaviour of pin sds/rsto in suspend/idle mode depends on its configuration in operational mode before suspend was entered. if the pin was used as rsto then it will be ?z? in suspend/idle mode, if it was used as sds then it keeps the output characteristic is suspend mode. 51xtal1 iii 52 xtal2 o o o 46test iii 66res_l iii table 9 pin definition - miscellaneous (cont ? d) pin no. symbol during reset in suspend mode in idle mode psb 2154 c800 microcontroller data sheet 27 2001-01-24 3 c800 microcontroller 3.1 cpu the cpu is designed to operate on bits and bytes. the instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. one machine cycle requires twelve microcontroller clock cycles. the instruction set has extensive facilities for data transfer, logic and arithmetic instructions. the boolean processor has its own full- featured and bit-based instructions within the instruction set. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. a machine cycle (12 microcontroller clocks) consists of 6 states. each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. the diagrams in figure 8 show the fetch/execute timing related to the internal states and phases. in emulation mode ( chapter 3.3.6 and chapter 3.4 ) ale is normally activated twice during each machine cycle: once during s1p2 and s2p1, and again during s4p2 and s5p1. this signal is used as cs during normal operation and is not toggling but stays active permanently during successive accesses. execution of a one-cycle instruction begins at s1p2, when the op-code is latched into the instruction register. if it is a 2-byte instruction, the second reading takes place during s4 of the same machine cycle. if it is a one-byte instruction, there is still a fetch at s4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. in any case, execution is completed at the end of s6p2. most c800 instructions are executed in one cycle. mul (multiply) and div (divide) are the only instructions that take more than 2 cycles to complete: they take 4 cycles. normally, 2 code bytes are fetched from the program memory every machine cycle. the only exception is when a movx instruction is executed. movx is a one-byte, 2-cycle instruction that accesses external data memory. during a movx, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. fetches from external program memory always use a 16-bit address. accesses to external data memory can use either a 16-bit address (movx @dptr) or an 8-bit address (movx @ri). for 8-bit addressing the xram page register (xpage) is used as the high byte, which allows effective addressing in critical loops: loop using 16-bit address: movx a, @dptr (2 cycles) inc dptr (2 cycles) loop_based_on_some_condition psb 2154 c800 microcontroller data sheet 28 2001-01-24 loop using 8-bit address: movx a, @ri (2 cycles) inc ri (1 cycle) loop_based_on_some_condition figure 8 fetch execute sequence c clock psb 2154 c800 microcontroller data sheet 29 2001-01-24 3.2 memory organisation the c800 cpu manipulates operands in the following address spaces: ? 4 kbyte onchip rom program memory (boot loader); see note ? 16 kbyte onchip ram (xram) memory for program and/or data (configurable ) ? extension for up to 64 kbyte internal/external program memory ? 256 bytes of internal data memory (iram) ? 128 byte special function register area ? extension for up to 62 kbyte internal/external data memory figure 9 illustrates the memory address spaces of the c800. figure 9 c800 default memory map (firmware execution mode) note: for simplification the 4k onchip rom is not shown in figure 9 but described in detail in figure 14 . off chip on chip (ea = 1) off chip (ea = 0) off chip isdn reg map (2kbyte) on chip xram off chip internal ram special function register internal ram 0000 h ffff h ffff h 0000 h ff h 7f h 80 h ff h 80 h 00 h program code space external data space internal data space indirect address direct address 2154_81.vsd 4000 h 3fff h f800 h f7ff h psb 2154 c800 microcontroller data sheet 30 2001-01-24 3.2.1 external memory address mapping if external memory is connected the internal 16k ram is used as program space. the internal addresses are shifted by 4000 h to external addresses, i.e. internal address 4000 h is mapped to external address 0000 h ( figure 10 ), so for external program space the higher 16k is not used due to the internal ram. data addresses are shifted by 4000 h similar as program space with the result that the lower 16k internal data addresses are mapped to the upper 16k external address. the 2k space corresponding to the isdn registers cannot be used in external memory. table 10 mapping of internal and external addresses internal address external address program 0000 h - 3fff h -- internal ram 4000 h - ffff h 0000 h - bfff h -- c000 h - ffff h not used data 0000 h - 3fff h c000 h - ffff h 4000 h - f7ff h 0000 h - b7ff h f800 h - ffff h -- isdn registers -- b800 h - bfff h not used psb 2154 c800 microcontroller data sheet 31 2001-01-24 figure 10 external memory address mapping program space 2154_42 on chip program --- internal ram 0000 h 16 kbyte off chip program --- external ram 48 kbyte 3fff h 4000 h ffff h isdn registers ffff h f800 h 2kbyte off chip data --- external ram 62 kbyte 0000 h f7ff h 3fff h 4000 h data space internal address map 48 kbyte c000 h ffff h 0000 h bfff h 16 kbyte external address map not used 46 kbyte c000 h ffff h 0000 h bfff h 16 kbyte not used b800 h b7ff h 2kbyte psb 2154 c800 microcontroller data sheet 32 2001-01-24 3.2.2 program memory the c800 has 4 kbyte of rom program memory which stores the download routines (boot loader). the firmware can be downloaded into onchip program ram, which can be externally expanded up to 64 kbytes in total. if the ea pin is held high, the c800 executes program code out of internal program memory till the program counter address exceeds internal program space. if the ea pin is held low, the c800 will fetch all instructions from an external 64 kbyte program memory (eprom mode) and the internal rom is ignored. note: for further details on memory configuration please refer to chapter 7.3 . 3.2.3 data memory the data memory address space consists of internal memory and external memory space. the internal data memory is divided into 3 physically separate and distinct blocks: the lower 128 bytes of ram, the upper 128 bytes of ram and the 128 byte special function register (sfr) area. the external data memory is divided into onchip xram and another 2 kbyte of address space reserved for isdn registers. offchip external data memory may be either 8-bit or 16-bit addressable. registers r0 and r1 are used for indirect 8-bit addressing. the dptr registers are used for 16-bit addressing. note: the registers of the usb module are accessed through special function registers in the sfr area. 3.2.4 general purpose registers - overview the lower 32 locations of the internal ram (data memory addresses from 00 to 1f) are assigned to 4 banks with 8 general purpose registers (gprs) each. only one of these banks may be enabled at a time. 2 bits in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank. this allows fast context switching, which is useful when entering subroutines or interrupt service routines. the 8 general purpose registers of the selected register bank may be accessed by register addressing. with register addressing, the instruction opcode indicates which register is to be used. for indirect addressing, r0 and r1 are used as pointer or index registers to address internal or external memory (e.g. mov @r0). reset initializes the stack pointer to location 07 and increments it once to start from location 08, which is also the first register (r0) of register bank 1. thus, if one is going to use more than one register bank, the sp should be initialized to a different location of the ram which is not used for data storage. 16 bytes of data memory (addresses 20 to 2f) are bit-addressable. direct addresses from 30 to 7f can be used as scratch pad registers or for a stack. psb 2154 c800 microcontroller data sheet 33 2001-01-24 3.2.5 special function registers - overview the registers, except the program counter, the four general purpose register banks and the isdn registers, reside in the special function register (sfr) area. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h ,..., f8 h ) are bit- addressable. the sfrs include pointers and registers that provide an interface between the cpu and other onchip peripherals. the sfrs are listed in table 11 and table 12 . in table 11 they are organised in functional groups. table 12 illustrates the contents of the sfrs in numeric order of their addresses. table 11 special function registers - functional blocks block symbol name addr contents after reset pag e no. bit add r cpu sp dpl dph dpsel psw acc b psiz dsiz syscon 1 syscon 2 xpage stack pointer data pointer, low byte data pointer, high byte data pointer selector program status word accumulator b register program ram size data ram size system control 1 system control 2 xram page 81 82 83 84 d0 e0 f0 ab bc ad a4 ae 07 00 00 00 00 00 00 06 0a 21 00 00 59 59 59 60 63 68 68 69 70 71 73 74 no no no no yes yes yes no no no no no interrupt system ien0 ien1 ien2 ip0 ip1 interrupt enable 0 interrupt enable 1 interrupt enable 2 interrupt priority 0 interrupt priority 1 a8 a9 aa b8 ac 00 00 00 00 00 306 307 307 313 313 yes no no yes no ports p0 p2 p3 port 0 port 2 port 3 80 a0 b0 ff ff ff 47 47 47 yes yes yes power pcon wcon power control wakeup control 87 8e 00 00 62 64 no no psb 2154 c800 microcontroller data sheet 34 2001-01-24 timers tcon tmod tl0 tl1 th0 th1 timer control timer mode timer 0, low byte timer 1, low byte timer 0, high byte timer 1, high byte 88 89 8a 8b 8c 8d 00 00 00 00 00 00 57 58 56 56 56 56 yes no no no no no spi eepint eepcmd eepadr eepdat eepsl eeprom interrupt control eeprom command eeprom byte address eeprom data eeprom start/load 93 94 95 96 97 00 00 00 00 00 299 353 354 354 355 no no no no no pll plcona plconb pll configuration a pll configuration b a1 a2 c1 80 66 66 no no hw config hcon memory mode boot mode system version number a3 mmod pin bmod pins svn pins 65 no table 11 special function registers - functional blocks (cont ? d) block symbol name addr contents after reset pag e no. bit add r psb 2154 c800 microcontroller data sheet 35 2001-01-24 usb module epsel usbval adroff gesr gepir ciari ciarie ciar dcr dpwdr dier dirr dsir dgsr fnrl fnrh epbcn epbsn epien epirn epban eplenn egsr ifcsel igsr endpoint select usb data address offset global endpoint stall global endpoint interrupt request flag config request interrupt config interrupt enable configuration request status device control device power down device interrupt enable device interrupt request device setup interrupt device get_status register frame number, low byte frame number, high byte endpoint n buffer control endpoint n buffer status endpoint n interrupt enable endpoint n interrupt request endpoint n base address endpoint n buffer length endpoint get_status register interface select interface get_status register d2 d3 d4 da d6 d7 d8 d9 c1 c2 c3 c4 c5 c9,c a c6 c7 c1 c2 c3 c4 c5 c6 c9,c a db cb,c c 80 00 00 00 00 00 00 00 000x0000 00 00 00 00 0000 xx 00000xxx 00 20 00 01 / 00 00 0xxxxxxx 0000 00 0000 108 110 111 107 303 304 310 112 113 115 308 299 301 117 116 116 119 120 309 301 122 123 124 109 118 no no no no no no no no no no no no no no no no no no no no no no no no no table 11 special function registers - functional blocks (cont ? d) block symbol name addr contents after reset pag e no. bit add r psb 2154 c800 microcontroller data sheet 36 2001-01-24 isdn register map (non sfr registers) isdn d and c/i channel registers ff00 - ff2f 227 no isdn transceiver registers ff30 - ff3b 244 no isdn auxiliary interface registers ff3c - ff3f 254 no isdn iom-2 and monitor handler ff40 - ff5f 257 no isdn interrupt & general configuration registers ff60 - ff6f 275 no isdn b-channel a registers ff70 - ff7f 281 no isdn b-channel b registers ff80 - ff8f no table 11 special function registers - functional blocks (cont ? d) block symbol name addr contents after reset pag e no. bit add r psb 2154 c800 microcontroller data sheet 37 2001-01-24 table 12 special function registers - numerically ordered addresses addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 p0 .7 .6 .5 .4 .3 .2 .1 .0 81 sp .7 .6 .5 .4 .3 .2 .1 .0 82dpl .7.6.5.4.3.2.1 .0 83dph .7.6.5.4.3.2.1 .0 84dpsel00000d2d1d0 87 pcon res. sms idls res. gf1 gf0 sme idle 88 tcon tf1 tr1 tf0 tr0 0 res. ie0 it0 89 tmod res. c/t 1 m1(1) m0(1) gate0 c/t 0 m1(0) m0(0) 8atl0 .7.6.5.4.3.2.1 .0 8btl1 .7.6.5.4.3.2.1 .0 8cth0 .7.6.5.4.3.2.1 .0 8dth1 .7.6.5.4.3.2.1 .0 8ewconewpd000wpuswpi0wpciwptr 93eepint0000000ecint 94eepcmd.7.6.5.4.3.2.1 .0 95eepadr.7.6.5.4.3.2.1 .0 96eepdat.7.6.5.4.3.2.1 .0 97eepsleld000000esta a0 p2 .7 .6 .5 .4 .3 .2 .1 .0 a1 plcona n4 n3 n2 n1 n0 m3 m2 m1 a2 plconb m0 0 0 pscval pscen lock swck pclk a3 hcon mmod bmod1 bmod0 svn4 svn3 svn2 svn1 svn0 a4syscon200000scsstat2stat1 a8 ien0 eal 0 ex5 es et1 res. et0 ex0 a9 ien1 0 0 ex11 ex10 ex9 ex8 ex7 ex6 aa ien2 0 0 res. res. res. ex14 ex13 ex12 abpsiz000.4.3.2.1.0 acip1 0 0 .5.4.3.2.1 .0 ad syscon1 0 0 eale 0 0 stat0 xmap1 xmap0 ae xpage .7 .6 .5 .4 .3 .2 .1 .0 psb 2154 c800 microcontroller data sheet 38 2001-01-24 b0 p3 .7 .6 .5 .4 .3 .2 .1 .0 b8ip0 0 0 .5.4.3.2.1 .0 bcdsiz000.4.3.2.1.0 c1 usb device and endpoint registers. see table 13 . c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc d0 psw cy ac gf3 rs1 rs0 ov gf2 p d2epseleps70000eps2eps1eps0 d3 usbval .7 .6 .5 .4 .3 .2 .1 .0 d4 adroff 0 0 ao5 ao4 ao3 ao2 ao1 ao0 d6 gepir epi7 epi6 epi5 epi4 epi3 epi2 epi1 epi0 d7ciari0000000drvi d8ciarie0000000drvie d9 ciar 0 0 cfg 0 ifc1 ifc0 0 as da gesr epst7 epst6 epst5 epst4 epst3 epst2 epst1 epst0 dbifcsel000000if1if0 e0acc .7.6.5.4.3.2.1 .0 f0b .7.6.5.4.3.2.1 .0 table 12 special function registers - numerically ordered addresses (cont ? d) addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 psb 2154 c800 microcontroller data sheet 39 2001-01-24 table 13 usb device and endpoint registers addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device registers (selected via epsel.eps7 = 1, eps2-0 = don ? t care) c1 dcr 0 da swr susp dinit rsm uclk 0 c2 dpwdr 0 0 0 0 0 0 tpwd rpwd c3 dier se0ie daie ddie sbie seie stie suie sofie c4 dirr se0i dai ddi sbi sei sti sui sofi c5 dsir 0 0 0 0 0 0 gsie gsir c6 fnrl fnr7 fnr6 fnr5 fnr4 fnr3 fnr2 fnr1 fnr0 c7 fnrh 0 0 0 0 0 fnr10 fnr11 fnr9 c8 reserved c9 dgsr dst7 dst6 dst5 dst4 dst3 dst2 rwup pstat ca dst15 dst14 dst13 dst12 dst11 dst10 dst9 dst8 cb igsr ist7 ist6 ist5 ist4 ist3 ist2 ist1 ist0 cc ist15 ist14 ist13 ist12 ist11 ist10 ist9 ist8 endpoint registers(8 sets of the registers below for endpoints 0...7, selected via epsel.eps7 = 0, eps2-0 = 000 b ... 111 b ) c1 epbc stall 0 0 gepie sofde ince 0 dbm c2 epbs ubf cbf dir esp setrd setwr clrep done c3 epie aie naie rleie 0 dnrie nodie eodie sodie c4 epir ack nack rle 0 dnr nod eod sod c5 epba page 0 0 0 an6 an5 an4 an3 c6 eplen 0 ln6 ln5 ln4 ln3 ln2 ln1 ln0 c7 reserved c8 reserved c9 egsr est7 est6 est5 est4 est3 est2 est1 stall ca est15 est14 est13 est12 est11 est10 est9 est8 psb 2154 c800 microcontroller data sheet 40 2001-01-24 3.3 external bus interface the c800 allows external memory expansion. it is possible to distinguish between access to external program memory and external data memory. this distinction is made by hardware using different interface connections. 3.3.1 interface signals the siuc uses the following address/data buses and control signals to connect external memory: accesses to external program memory use the signal psen (program store enable) as a read strobe during normal operation . the program write signal pwr is only used to load the firmware into external program memory (firmware download ) if separate memory devices for program and data are used (mmod=1). for this purpose the internal write signal of the c is switched from the wr pin (normal mode; syscon1.scs=0) to the pwr pin (download mode; syscon1.scs=1) which also switches the internal read signal from the psen pin to the rd pin (for read-back during download mode). accesses to external data memory use rd and wr to strobe the memory. port 0 is used as bidirectional data bus. the address is output on port 2 (msb-address) and a0-7 (lsb-address). the cs signal is used to select external program and data memory. it is inactive during accesses to internal xram and in suspend mode (reduces power consumption of sram). for successive external accesses the cs signal is not toggling but stays active permanently until the next internal access occurs. 3.3.2 shared and separate external memories external memory for program and data is connected to the data and address buses while the access is differentiated by using individual control signals. this is called "separate memory concept" in this specification and is indicated to the c by pin mmod=1 ( figure 12 ). however, mmod has no direct effect on the hw functions of siuc, but control of certain signals of the memory interface must be done by the c. in some applications it is desirable to use only one memory device and to execute program from the same physical memory that is used for storing data, i.e. using "shared memory". this is indicated by pin mmod=0. for this case the c800 provides the option of a combined read strobe signal for program (psen ) and data (rd ) access on a single pin rd , so an external and gate can be saved. psb 2154 c800 microcontroller data sheet 41 2001-01-24 figure 11 shared and separate external memory expansion 3.3.3 switching of control signals the read strobe signals to external program and data memory spaces can internally be combined by a logical and of psen and rd by setting syscon1:stat0=1 ( figure 12 ). this operation produces a combined active low read strobe at pin rd that can be used for the program/data access in one single memory. since the psen cycle is faster than the rd cycle, the external memory needs to be fast enough to adapt to the psen cycle. figure 12 switching of read strobe signals for shared memory a.0-7 p2.0-7 a0-7 a8-15 p0.0-7 d0-7 p3.2 / wr p3.3 / rd psen wr oe cs external memory (prog and data) shared external memory, mmod=0 (program and data in one single memory) a0-7 a8-15 d0-7 wr oe cs separate external memory, mmod=1 (program and data in separate memories) external memory (data) a0-7 a8-15 d0-7 external memory (program) 2154_69 a.0-7 p2.0-7 p0.0-7 ale / cs p3.3 / rd psen p3.4 / pwr wr oe cs p3.2 / wr ale / cs p3.4 / pwr "xxx" = internal signals stat0=0 separate memory stat0=1 shared memory "rd" rd pwr "psen" psen "wr" wr syscon1.stat0 1 0 2154_39.vsd psb 2154 c800 microcontroller data sheet 42 2001-01-24 with separate external memories read/write access can be performed to data memory and read access to program memory (opcode fetch) by default ( figure 13 a ). during firmware download to external program memory write access can be enabled by setting syscon1.scs=1. the internal read and write strobe signals are connected to the psen and pwr pins so the external program space is accessed like data memory. the internal psen signal is not available outside and the pins rd and wr are inactive. the scs bit is not controlled by the the siuc automatically but has to be set/reset by the microcontroller as required. figure 13 switching of read/write strobe signals for separate memory 3.3.4 enabling of xram access and memory ports / signals after reset the access to onchip xram is disabled, i.e. the c must set bit syscon1.xmap0=1 in order to enable internal xram access , otherwise all accesses to these locations are driven on the external memory bus. for normal operation the memory ports port 0 and port 2 and the control signals rd , wr and ale/cs are disabled during accesses to onchip xram. for test purposes they can also be enabled during internal access. the output of ale/cs is disabled during internal access by resetting syscon1.eale to "0" (default is "1"). port 0, port 2, rd and wr can be enabled during internal access by setting syscon1.xmap1 to "1" (default is "0"). "rd" rd "wr" wr pwr "psen" psen a) syscon2.scs=0 "rd" rd "wr" wr pwr "psen" psen b) syscon2.scs=1 2154_39.vsd psb 2154 c800 microcontroller data sheet 43 2001-01-24 3.3.5 partitioning of ram, switching from rom to ram in download mode the bootloader contained in rom performs the download of the firmware to internal/external ram ( figure 14 ). the 16k internal ram which can be extended by connected memory, is used as data ram where the c writes the downloaded data to. after the download is finished the c first partitions the internal ram, if required, by writing the psiz and dsiz registers. then it sets the bit syscon2.stat2=1 to switch from rom to ram and with a successive register access setting syscon2.stat1=1 a reset to the c is performed which has the effect that the program counter starts execution in ram at address 0000 h . the siuc allows various memory configurations (for details see chapter 7.3 ). the onchip 16k ram can be extended by connecting program and data memory ( figure 14 , example 1 ). for single chip mode (no memory extension) the onchip 16k ram can flexibly be configured to be used as program and data memory depending on system requirements ( figure 14 , example 2 ). after switching from rom to ram (see above) the c configures the partitioning of program and data memory in the psiz and dsiz registers. the data memory partition is always located right below the isdn register set. the sum of psiz and dsiz must not exceed 16k. psb 2154 c800 microcontroller data sheet 44 2001-01-24 figure 14 switching from download mode to operational mode download mode c execution from rom (stat2=0) "program space" 2154_41 on chip data --- internal ram 16 k "data space" off chip data --- external ram (optional) 48 k on chip program --- rom download fw 4k normal mode - c execution from ram (stat2=1) "program space" "data space" off chip data (optional) 62 k on chip rom 4k isdn 2k off chip program (optional) 48 k not visible ! "program space" "data space" off chip data (not used) 52 k on chip rom 4k on chip program 6k isdn 2k on chip data 10 k off chip program (not used) 58 k not visible ! on chip program 16 k example 2 example 1 psb 2154 c800 microcontroller data sheet 45 2001-01-24 3.3.6 external bus interface during emulation during emulation (also see chapter 3.4 ) the external memory interface is used in a different way than during normal operation which is described above. the major differences are: port 0 is used as multiplexed port for the lsb address and the data byte pin ale/cs is used as address latch enable for port 0 address port a0-7 is not used during emulation when used for accessing external memory, port 0 provides the data byte time- multiplexed with the low byte of the address. in this state, port 0 is disconnected from its own port latch, and the address/data signal drives both fets in the port 0 output buffers. thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. during any access to external memory, the cpu writes ff h to the port 0 latch (the sfr), thus obliterating whatever information the port 0 sfr may have been holding. whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. during this time, the port 2 lines are disconnected from the port 2 latch (the sfr). if an 8-bit address is used (movx @ri), the contents of the port 2 sfr remain at the port 2 pins throughout the external memory cycle. the timing of the external bus interface, in particular the relationship between the control signals ale, psen , rd , wr and information on port 0 and port 2, is illustrated in figure 15 a and b. data memory: in a write cycle, the data to be written appears on port 0 just before wr is activated and remains there until after wr is deactivated. in a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. program memory: signal psen functions as a read strobe. psb 2154 c800 microcontroller data sheet 46 2001-01-24 figure 15 external program memory execution pcl out pch out one machine cycle one machine cycle in inst. in out pcl pcl out in in out pcl in (a) without movx pcl out valid pcl out valid pcl out valid pcl out valid ale psen rd p2 a) b) p2 rd psen ale valid pcl out valid dpl or ri valid pcl out movx with (b) in pcl out in data in in dph out or p2 out one machine cycle one machine cycle out pcl s6 s5 s4 s3 s2 s1 s6 s5 s4 s3 s2 s1 mct03220 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 out pch pch out out pch pch out out pch inst. inst. inst. inst. p0 p0 inst. inst. inst. psb 2154 c800 microcontroller data sheet 47 2001-01-24 3.3.7 port structures the siuc-x has two 8-bit i/o ports (port 0 and port 2) and one 5-bit i/o port (port 3) which are described in this chapter. another 8-bit auxiliary i/o port (aux) is described in chapter 8.3 . port 0 is an open-drain bidirectional i/o port, while ports 2 and 3 are quasi-bidirectional with internal pullup resistors. that means, when configured as inputs, ports 2 and 3 will be pulled high and source current when externally pulled low. port 0 will float when configured as input. the output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. each port bit consists of a latch, an output driver and an input buffer. read and write accesses to the i/o ports are performed via their corresponding special function registers. figure 16 shows a functional diagram of a typical bit latch and i/o buffer, which is the core of each port cell. the bit latch (one bit in the port ? s sfr) is represented as a type- d flip-flop, which will clock in a value from the internal bus in response to a "write-to- latch" signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the cpu. the level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the cpu. some instructions that read from a port (i.e. from the corresponding port sfr) activate the "read-latch" signal, while others activate the "read-pin" signal. figure 16 basic structure of a port mcs01822 d clk port latch q q port read latch to latch read pin write int. bus port driver circuit pin psb 2154 c800 microcontroller data sheet 48 2001-01-24 alternate functions the pins of port 3 are multifunctional. they are port pins and also serve to implement special features as listed in table 14 . figure 17 shows a functional diagram of a port latch with alternate function. to pass the alternate function to the output pin and vice versa, the gate between the latch and driver circuit must be open. thus, to use the alternate input or output functions, the corresponding bit latch in the port sfr has to contain a logic 1; otherwise the pulldown transistor is on and the port pin stuck at 0. after reset, all port latches contain 1s. figure 17 port alternate function table 14 alternate functions of port 1 port pin alternate function p3.0 dadd device attached input of the usb module p3.1 int0 external interrupt 0 input p3.2 wr external data memory write strobe p3.3 rd external data memory read strobe p3.4 pwr external program memory write strobe mcs01827 d clk bit latch q q internal pull up arrangement pin read latch to latch read pin write v cc int. bus alternate output function alternate input function & psb 2154 c800 microcontroller data sheet 49 2001-01-24 3.4 enhanced hooks emulation concept the enhanced hooks emulation concept of the c800 family, which is similar to the c500 microcontroller series, is an innovative way to control the execution of the c800 cpu and to gain extensive information on the internal operation of the controllers. the siuc-x has built in logic for the support of this emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensures that emulation and production chips are identical. the enhanced hooks technology allows the c800 together with an eh-ic (custom developed for the siuc-x) to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-(in circuit emulation) system. different operating modes can be emulated, e.g. program rom, program rom with code rollover and romless mode. it is also able to operate in single step mode and to read the sfrs after a break. it should be noted, however, that during all these modes, code from the onchip program memory is never used. figure 18 basic c800 mcu enhanced hooks concept configuration mcs02647 syscon pcon tcon reset ea psen ale port 0 port 2 i/o ports optional port 3 port 1 c500 mcu interface circuit enhanced hooks rport 0 rport 2 rtcon rpcon rsyscon tea ta l e tpsen eh-ic target system interface ice-system interface to emulation hardware c800 mcu psb 2154 c800 microcontroller data sheet 50 2001-01-24 the enhanced hooks emulation concept is based on the following major functions: transfer of information about internal c operations to the eh-ic. c output pins that are required for emulation are duplicated by the external hardware, continuously. mapping of onchip program memory to emulation hardware. control of c status (run/break/stop modes) by emulation hardware. port 0, port 2 and some of the control lines of the c800 based mcu are used to control operation of the device during emulation and to transfer data and information about program execution between the external emulation hardware (ice-system) and the c800 mcu. reset and ea function as i/os in emulation mode. the emulation mode of the c800 is invoked by the eh-ic by driving certain pins (port 2, ale, psen , ea ) during reset to specific levels. for this reason, psen and ale and port 2 have internal pullup resistors, which are switched on during reset to ensure desired levels. figure 18 shows the enhanced hooks configuration for siemens c500 microcontroller series, which is the same for the c800 c. restrictions the c has the following restrictions in enhanced hooks emulation mode (not valid for normal operation mode): the programmable software reset (syscon2.stat1) is not supported. read-modify-write operations (e.g. anl p0, #0f h or orl p0, #0f h ) are not supported. however, the following workaround can be used, e.g. instead of anl p0, #f0 h : mov a, p0 anl a, #0f h mov p0, a psb 2154 c800 microcontroller data sheet 51 2001-01-24 3.5 timer 0 and 1 the siuc-x contains four timers, two 16-bit timers embedded in the c800 which are described below, and another two timers in the isdn section described in chapter 5.1.1 . the c800 contains two 16-bit timers, timer 0 and 1, which are useful in many applications. the timer register is incremented every machine cycle. thus one can think of it as counting machine cycles. since a machine cycle consists of 12 oscillator periods, the counter rate is 1/12 of the oscillator frequency. the timers 0 and 1 of the c800 are fully compatible with timers 0 and 1 of the 80c51 and can be used in the same four operating modes: mode 0: 8-bit timer with a divide-by-32 prescaler (m1=0; m0=0) mode 1: 16-bit timer (m1=0; m0=1) mode 2: 8-bit timer with 8-bit auto-reload (m1=1; m0=0) mode 3: timer 0 is configured as two 8-bit timers; timer 1 in this mode holds its count. the effect is the same as setting tr1 = 0. (m1=1; m0=1) the external input int0 can be programmed to function as a gate for timer 0 to facilitate pulse width measurement. each timer consists of two 8-bit registers (th0 and tl0 for timer 0, th1 and tl1 for timer 1) which may be combined to one timer configuration depending on the mode that is selected. the functions of the timers are controlled by two special function registers tcon and tmod. in the following descriptions the symbols th0 and tl0 are used to specify the high-byte and the low-byte of timer 0 (th1 and tl1 for timer 1, respectively). the operating modes are similar for both timers, except timer 0 only provides the gate function (bit gate0) with the external signal int0 . the timers are fully compliant to the c500 series of microcontrollers (e.g. c501). psb 2154 c800 microcontroller data sheet 52 2001-01-24 3.5.1 mode 0 putting timer 0 and 1 into mode 0 configures it as an 8-bit timer with a divide-by-32 prescaler ( figure 19 ). in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1 ? s to all 0 ? s, it sets the timer overflow flag tfx (x = 0 or 1). the overflow flag tfx then can be used to request an interrupt. the counted input is enabled to the timer when trx = 1 and either gate0 = 0 or int0 = 1 (setting gate0 = 1 allows the timer to be controlled by external input int0 , to facilitate pulse width measurements; for timer 0 only). trx is a control bit in the special function register tcon; bit gate0 is in tmod. the 13-bit register consists of all 8 bits of thx and the lower 5 bits of tlx. the upper 3 bits of the tlx register are indeterminate and should be ignored. setting the run flag (trx) does not clear the registers. mode 0 operation is similar for timer 0 and timer 1, however only for timer 0 there is the gate bit gate0 and the external signal int0 . figure 19 timer mode 0: 13-bit timer 2154_44 tf0 th0 (8 bits) interrupt tl0 (5 bits) :12 osc no clock / timer halted c/t0 = 0 & tr0 1 > _ =1 gate0 p3.2 / int0 tf1 th1 (8 bits) interrupt tl1 (5 bits) :12 osc no clock / timer halted tr1 c/t0 = 1 c/t1 = 0 c/t1 = 1 control control timer 0 timer 1 psb 2154 c800 microcontroller data sheet 53 2001-01-24 3.5.2 mode 1 mode 1 is the same as mode 0, except that the timer register is running with all 16 bits ( figure 20 ). figure 20 timer mode 1: 16-bit timer 2154_45 tf0 th0 (8 bits) interrupt tl0 (8 bits) :12 osc no clock / timer halted c/t0 = 0 & tr0 1 > _ =1 gate0 p3.2 / int0 tf1 th1 (8 bits) interrupt tl1 (8 bits) :12 osc no clock / timer halted tr1 c/t0 = 1 c/t1 = 0 c/t1 = 1 control control timer 0 timer 1 psb 2154 c800 microcontroller data sheet 54 2001-01-24 3.5.3 mode 2 mode 2 configures the timer register as an 8-bit counter (tlx) with automatic reload, as shown in figure 21 . overflow from tlx not only sets tfx, but also reloads tlx with the contents of thx, which is preset by software. the reload leaves thx unchanged. figure 21 timer mode 2: 8-bit timer with auto-reload 2154_46 tf0 th0 (8 bits) interrupt tl0 (8 bits) :12 osc no clock / timer halted c/t0 = 0 & tr0 1 > _ =1 gate0 p3.2 / int0 :12 osc no clock / timer halted tr1 c/t0 = 1 c/t1 = 0 c/t1 = 1 reload control control tf1 th1 (8 bits) interrupt tl1 (8 bits) reload timer 0 timer 1 psb 2154 c800 microcontroller data sheet 55 2001-01-24 3.5.4 mode 3 mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1=0. timer 0 in mode 3 establishes tl0 and th0 as two seperate counters. the logic for mode 3 on timer 0 is shown in figure 22 . tl0 uses the timer 0 control bits: c/t 0, gate0, tr0, int0 and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the ? timer 1 ? interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself. figure 22 timer mode 3: two 8-bit timers 2154_47 tf0 interrupt tl0 (8 bits) :12 osc no clock / timer halted c/t0 = 0 & tr0 1 > _ =1 gate0 p3.2 / int0 :12 osc tr1 c/t0 = 1 control control tf1 interrupt th0 (8 bits) timer 0 timer 1 psb 2154 c800 microcontroller data sheet 56 2001-01-24 3.6 timer 0 and 1 registers totally six special function registers control the timer 0 and 1 operation : tl0/th0 and tl1/th1 - counter registers, low and high part tcon and tmod - control and mode select registers 3.6.1 tlx / thx - timer low / high registers resetvalue:00 h address: 8a h resetvalue:00 h address: 8b h resetvalue:00 h address: 8c h resetvalue:00 h address: 8d h 76543210 tl0 rw rw rw rw rw rw rw rw 76543210 tl1 rw rw rw rw rw rw rw rw 76543210 th0 rw rw rw rw rw rw rw rw 76543210 th1 rw rw rw rw rw rw rw rw psb 2154 c800 microcontroller data sheet 57 2001-01-24 3.6.2 tcon - timer control register resetvalue:00 h address: 88 h the timer control register (tcon) is also described in the section on interrupts. bit function tlx.7-0 x=0-1 timer 0/1 low register thx.7-0 x=0-1 timer 0/1 high register 76543210 tf1 tr1 tf0 tr0 0 res. ie0 it0 r rw r rw r rw r rw bit function tr0 timer 0 run control bit set/cleared by software to turn timer 0 on/off. tf0 timer 0 overflow flag set by hardware on timer overflow. cleared by hardware when processor vectors to interrupt routine. tr1 timer 1 run control bit set/cleared by software to turn timer 1 on/off. operating mode description 0 ? tlx ? holds the 5-bit prescaler value. 1 ? tlx ? holds the lower 8-bit part of the 16-bit timer value. 2 ? tlx ? holds the 8-bit timer value. 3 tl0 holds the 8-bit timer value; tl1 is not used. operating mode description 0 ? thx ? holds the 8-bit timer value. 1 ? thx ? holds the higher 8-bit part of the 16-bit timer value 2 ? thx ? holds the 8-bit reload value. 3 th0 holds the 8-bit timer value; th1 is not used. psb 2154 c800 microcontroller data sheet 58 2001-01-24 note: res. = bit is reserved and must not be changed. 3.6.3 tmod - timer mode register resetvalue:00 h address: 89 h timer 1 control: c/t 1, m1-0(1) timer 2 control: gate0, c/t 0, m1-0(0) tf1 timer 1 overflow flag set by hardware on timer overflow. cleared by hardware when processor vectors to interrupt routine. ie0 external interrupt 0 edge flag set by hardware when an external interrupt condition at pin int0 is detected (low level if it0=0 or falling edge if it0=1) it0 interrupt 0 control bit if 1, a falling edge triggers an interrupt; if 0, a low level triggers an interrupt. 76543210 res. c/t 1 m1(1) m0(1) gate0 c/t 0 m1(0) m0(0) rw rw rw rw rw rw rw rw bit function c/t x (x=0, 1) timer x selector 0: input is from internal system clock. 1: no input clock (timer is halted). gate0 timer 0 gate flag 0: timer 0 is enabled whenever tcon.tr0 is set to ? 1 ? (software control). 1: timer 0 is enabled only if tcon.tr0 is set to ? 1 ? and if the int0 pin is set to ? 1 ? (hardware control). bit function psb 2154 c800 microcontroller data sheet 59 2001-01-24 note: res. = bit is reserved and must not be changed. 3.7 microcontroller registers stack pointer the sp register (address 81 h ) contains the stack pointer. the stack pointer is used to load the program counter into memory during lcall and acall instructions and is used to retrieve the program counter from memory in ret and reti instructions. the stack may also be saved or loaded using push and pop instructions, which also increment and decrement the stack pointer. the stack pointer points to the top location of the stack. on reset, the stack pointer is set to 07 h . general purpose flags the siuc provides 4 general purpose flags gf3-0 which can be read/written by the microcontroller without effect on any function of the siuc. their value is only set to their default value with a reset, otherwise it ? s only changed by a c write access. gf0 and gf1 are located in the pcon register, gf2 and gf3 are part of the psw register. m1-0 (x) (x= 0, 1) timer x mode control bit m1-0 m1 m0 function 0 0 8-bit timer: ? thx ? operates as 8-bit timer ? tlx ? serves as 5-bit prescaler 0 1 16-bit timer. ? thx ? and ? tlx ? are cascaded; there is no prescaler 1 0 8-bit auto-reload timer. ? thx ? holds a value which is to be reloaded into ? tlx ? each time it overflows 1 1 timer 0 : tl0 is an 8-bit timer controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. timer 1 : timer 1 stops psb 2154 c800 microcontroller data sheet 60 2001-01-24 3.7.1 dpsel - data pointer select register the microcontroller architecture provides 8 16-bit pointers for indirect addressing of external devices, for offset code byte fetches and for offset program jumps. the current data pointer is given by the contents of the data pointer high (dph) register and the data pointer low (dpl) register (see chapter 3.7.2 ). the 3 least significant bits of the dpsel register are used to select among the 8 data pointers dptr0 - dptr7. resetvalue:00 h address: 84 h the addresses of the dph and dpl registers remain 83h and 82h, respectively, under all conditions. figure 23 illustrates the access mechanism. 76543210 00000 d2d1d0 r r r r r rw rw rw bit function d2 - d0 data pointer select bits 000: dptr0 selected (default after reset) 001: dptr1 selected 010: dptr2 selected 011: dptr3 selected 100: dptr4 selected 101: dptr5 selected 110: dptr6 selected 111: dptr7 selected psb 2154 c800 microcontroller data sheet 61 2001-01-24 3.7.2 data pointer register low / high - dpl / dph resetvalue:00 h address: 82 h resetvalue:00 h address: 83 h figure 23 external data memory access (onchip & offchip) via 8 data pointers 76543210 dpl rw rw rw rw rw rw rw rw 76543210 dph rw rw rw rw rw rw rw rw dph(83 ) dpl(82 ) dptr0 dptr7 .0 .1 .2 - - - - - dpsel(92 ) dpsel selected data- pointer .2 .1 .0 dptr 0 0 0 0 0 0 1 dptr 1 0 1 0 dptr 2 0 1 1 dptr 3 1 0 0 dptr 4 1 0 1 dptr 5 1 1 0 dptr 6 1 1 1 dptr 7 mcd00779 external data memory h hh dpsel(84 h ) psb 2154 c800 microcontroller data sheet 62 2001-01-24 3.7.3 pcon - power control register resetvalue:00 h address: 87 h note: res. = bit is reserved and must not be changed. 76543210 res. sms idls res. gf1 gf0 sme idle rw rw rw rw rw rw rw rw bit function sms suspend mode start when set to 1, power-down (suspend) mode is started, provided sme (pcon.1) was set by the previous instruction. the bit is then automatically cleared by hardware. it always returns 0 when read. the power down state is described in chapter 9.2.2 . idls idle start when written to 1, idle mode is started, provided idle (pcon.0) was set by the previous instruction. the bit is then automatically cleared by hardware. it always returns a 0 when read. the idle state is described in chapter 9.2.1 . gf1 general purpose flag 1 gf0 general purpose flag 0 sme suspend mode enable writing a 1 starts a delay cycle whereby the following instruction can put the core into power-down mode by writing a 1 to pcon.6 (sms). the bit is then automatically cleared by hardware. it always returns a 0 when read. idle idle mode enable writing a 1 starts a delay cycle whereby the following instruction can put the core into idle mode by writing a 1 to pcon.5 (idls). the bit is then automatically cleared by hardware. it always returns a 0 when read. psb 2154 c800 microcontroller data sheet 63 2001-01-24 3.7.4 psw - program status word register the program status word register contains status information resulting from cpu and alu operations. resetvalue:00 h address: d0 h 76543210 cy ac gf3 rs1 rs0 ov gf2 p rw rw rw rw rw rw rw rw bit function cy alu carry flag ac alu auxiliary carry flag gf3 general purpose flag 3 rs1,rs0 register bank select bit 1,0 rs1=0, rs0=0: rb0. registers from 00 - 07 h . rs1=0, rs0=1: rb1. registers from 08 - 0f h . rs1=1, rs0=0: rb2. registers from 10 - 17 h . rs1=1, rs0=1: rb3. registers from 18 - 1f h . ov alu overflow flag gf2 general purpose flag 2 p parity flag set each instruction cycle to indicate odd/even parity in the accumulator. psb 2154 c800 microcontroller data sheet 64 2001-01-24 3.7.5 wcon - wakeup control register resetvalue:00 h address: 8eh note: setting to ? 1 ? means ? enabled ? , setting to ? 0 ? means ? disabled ? . for further information see chapter 6.3 and chapter 9.3.6 . 76543210 ewpd 0 0 0 wpus wpi0 wpci wptr rw r r r rw rw rw rw bit function ewpd external wakeup from power down enable setting ewpd before entering power down mode enables the external wakeup capability from power down mode, via the pin p3.1/int0 , the usb module, the s-transceiver, a c/i code change or from one of the interrupt signals int1 , int2 or eaw . each of the four groups of sources can individually be enabled. however, enabling one of the four wakeup sources (wpus, wpio, wpci or wptr) has no effect if ewpd is not set to ? 1 ? at the same time. wpus wakeup via usb bus enabled any activity on the bus (usb resume) will wakeup the siuc-x from suspend mode. in normal operation mode this event is indicated in the interrupt status bit dirr.sei. wpi0 wakeup via p3.1/int0 enabled an active signal on pin int0 will wakeup the siuc-x from suspend mode. in normal operation mode this event is indicated in the interrupt status bit tcon.ie0 wpci wakeup via c/i-code change, eaw or int1/2 interrupt pins enabled a c/i-code change or an active signal on one of the interrupt pins eaw , int1 or int2 will wakeup the siuc-x from suspend mode. in normal operation mode these events are indicated in the corresponding interrupt status bits ista.cic, auxi.eaw and auxi.int1/2, respectively. wptr wakeup via s-transceiver level detect enabled any activity on the s bus will wakeup the siuc-x from suspend mode. in normal operation mode this event is indicated in the interrupt status bit istatr.ld. psb 2154 c800 microcontroller data sheet 65 2001-01-24 3.7.6 hcon - hardware configuration register resetvalue:00 h address: a3 h the hcon register is transferred to the host after power on reset by means of a string descriptor. the values can be used by the host to uniquely identify the system configuration built around the siuc in order to select the appropriate firmware and driver software. 76543210 mmod bmod1 bmod0 svn4 svn3 svn2 svn1 svn0 r r r rw rw rw rw rw bit function mmod memory mode the state of pin mmod is latched during reset and can be read from this bit position. it indicates the external memory mode: 0: program and data is located in the same physical memory device. 1: program and data is stored in physically different memories. this bit has no direct effect on the hw functions of the siuc. bmod1- bmod0 boot mode the state of the boot mode pins is available at this address. bmod1/0 together with pin ea determine in which operation mode the c starts after reset (see chapter 7.1 ) svn4-0 system version number these bits have no effect on the functions of the device but they can be used to identify different hardware configurations as this number is forwarded to the host for identification purposes. svn1-0: the state of the svn1 and svn0 pins is latched during reset and can be read from this bit position. if an eeprom is connected, the c overwrittes these bits with a system version number loaded from the eeprom. svn4-2: if an eeprom is connected, the c overwrittes these bits with a system version number loaded from the eeprom. if no eeprom is connected these bits keep their reset values (000 b ). psb 2154 c800 microcontroller data sheet 66 2001-01-24 3.7.7 plcona/b - pll configuration registers a, b resetvalue:c1 h address: a1 h resetvalue:80 h address: a2 h 76543210 plcona n4 n3 n2 n1 n0 m3 m2 m1 rw rw rw rw rw rw rw rw 76543210 plconb m0 0 0 pscval pscen lock swck pclk rw r r rw rw r rw rw bit function n4 - n0 factor n determines the multiplication factor of the internal pll. values between 0 and 31 are possible (default = 24 d => multiplication by 25) m3 - m0 factor m determines the division factor of the internal pll. values between 0 and 15 are possible (default = 3 d => division by 4) pscval prescaler value the clock for the microcontroller is devided by a prescaler if pscen=1: 0: c clock divided by 2 1: c clock divided by 1.5 pscval has no effect if pscen=0 (prescaler disabled). pscen prescaler enable setting this bit to 1 enables the prescaler which is configured in pscval. lock pll locked when 0, the pll frequency is not stabilized and setting of bit swck is not allowed. when 1, the pll frequency has stabilized and the setting of bit swck is allowed. psb 2154 c800 microcontroller data sheet 67 2001-01-24 please also refer to chapter 8.1 . swck switch clock when 0, the pll is bypassed and the output clock is equal to the input clock. when 1, the output clock of the pll is derived from the input clock according to the following equation: pclk pll clock enable bit pclk controls the 48 mhz pll. if pclk=0, the 48 mhz pll is disabled (default after reset). if pclk=1, the 48 mhz pll is enabled as the pll is disabled after reset, the microcontroller and usb blocks are clocked at crystal speed (7.68 mhz). for normal operation the pll has to be programmed first. bit function output n1 + m1 + -------------- input = psb 2154 c800 microcontroller data sheet 68 2001-01-24 3.7.8 acc / b - accumulator / b register the accumulator (acc) provides one of the operands for most alu operations. the b register (b) provides the second operand for multiply or divide instructions. at other times, it may be used as a scratch pad register. resetvalue:00 h address: e0 h resetvalue:00 h address: f0 h 76543210 acc rw rw rw rw rw rw rw rw 76543210 b rw rw rw rw rw rw rw rw psb 2154 c800 microcontroller data sheet 69 2001-01-24 3.7.9 psiz - program ram size register the psiz and dsiz registers partition the onchip 16 kbyte ram into program space and data space. their contents are valid only in certain firmware modes as described in chapter 7 . resetvalue:06 h address: ab h 76543210 0 0 0 .4 .3 .2 .1 .0 r r r rw rw rw rw rw bit function psiz.4 - psiz.0 program ram allocation these bits define the size of the program ram within the 16 kbyte internal ram. the selection of pram size has a granularity of 1 kbyte. 00 h : no program ram is preset. 01 h : 1 kbyte program ram is present. 02 h : 2 kbyte program ram is present. . . 10 h - 1f h : 16 kbyte program ram is present. psb 2154 c800 microcontroller data sheet 70 2001-01-24 3.7.10 dsiz - data ram size register resetvalue:0a h address: bc h note: the sum of psiz and dsiz must not exceed the internal ram space of 16 kbyte. 76543210 0 0 0 .4 .3 .2 .1 .0 r r r rw rw rw rw rw bit function dsiz.4 - dsiz.0 data ram allocation these bits define the size of the data ram within the 16 kbyte internal ram. the selection of dram size has a granularity of 1 kbyte. 00 h : no data ram is preset. 01 h : 1 kbyte data ram is present. 02 h : 2 kbyte data ram is present. . . 10 h - 1f h : 16 kbyte data ram is present. psb 2154 c800 microcontroller data sheet 71 2001-01-24 3.7.11 syscon1 - system control register 1 resetvalue:21 h address: ad h 76543210 0 0 eale 0 0 stat0 xmap1 xmap0 r r rw r r rw rw rw bit function eale ale output control eale=0: the ale output pin is disabled during internal program memory accesses. eale=1: the ale output is enabled during internal program memory accesses(default after reset). for external access ale is always enabled, i.e. this bit has no effect on external memory accesses. stat0 status bit 0 this bit can be used in case a single external memory for program and data access should be used. when this bit is set to 1, a gated (anded) rd and psen signal is available at the rd pin which can directly be connected to the oe pin of the external memory. xmap1 xram visible access control xmap1=0: ports 0, 2, rd and wr pins are not activated during accesses to the onchip xram (default after reset). xmap1=1: ports 0, 2, rd and wr are activated during accesses to onchip xram. in this mode, address and data information during onchip xram accesses are visible externally. this mode should not be selected for normal operation. this bit has no effect during the emulation modes. all xram accesses are visible at the port pins during emulation. additionally, the rd and wr are always disabled for internal accesses during emulation modes. psb 2154 c800 microcontroller data sheet 72 2001-01-24 please also refer to chapter 3.3 . xmap0 global xram access enable/disable control xmap0=0: the access to onchip xram is enabled. xmap0=1: the access to onchip xram is disabled (default after reset). all movx accesses are performed via the external bus. after reset the c starts program execution from internal rom (ea =1) or from external rom (ea =0). the xmap0 bit must be set to 0 before any access to xram address space (download to 16k internal ram, or access to isdn registers) can be performed. once cleared, this bit can only be set again by a reset operation on the device. psb 2154 c800 microcontroller data sheet 73 2001-01-24 3.7.12 syscon2 - system control register 2 resetvalue:00 h address: a4 h 76543210 00000scsstat2stat1 rrrrrrwrwrw bit function scs switch memory control signals setting this bit to "1" has the effect that the internal data read/write signals are not output on pins rd /wr but on psen /pwr . the rd /wr pins are inactive and the psen signal is not available outside the chip. this mode is used during firmware download, so the c can access external program memory in a similar way as data memory. stat2 status bit 2 this bit is used to switch executable firmware: 0: the boot loader in internal rom is connected to the c 1: the operational firmware in ram is connected to the c this bit is only activated with the rising edge of syscon2.stat1, i.e. for switching of firmware from rom to ram, first the stat2 bit must be set to 0 or 1 and then with a consecutive register access the stat1 bit must be set to 1. this bit is not reset to its default value if stat1 is set (c reset), but the programmed value is retained and can be read back after the reset. stat1 status bit 1 this bit is the software reset bit for the c. setting it to 1 initiates a reset to the c and all its special function registers (sfr). this bit is automatically reset by the hardware. psb 2154 c800 microcontroller data sheet 74 2001-01-24 3.7.13 xpage - xram page register resetvalue:00 h address: ae h for further information refer to chapter 3.1 . 76543210 .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw bit function xpage.7 - xpage.0 xram high address byte the contents of this register are used as the high byte of the xram address for paged accesses, for 8-bit movx instructions with ri (i=0,1). psb 2154 usb module data sheet 75 2001-01-24 4 usb module the usb module handles all transactions between the universal serial bus usb and the internal (parallel) bus of the microcontroller. the usb module includes several units which are required to support data handling with the usb bus: an onchip usb bus transceiver a usb memory with 2 pages of 128 bytes each the memory management unit (mmu) for usb and c memory access control the usb device core (udc) for usb protocol handling a c interface with the usb specific special function registers and interrupt control logic figure 24 shows the block diagram of the functional units of the usb module with their interfaces. figure 24 usb module block diagram transceiver (on-chip) usb device core udc interrupt generation memory management unit mmu page 0 usb memory (128 x8 ) sfr addr. uc interface page 1 00 h 7f h 00 h 7f h internal bus pin pin d+ d- oscillator 7.68 mhz pin pin xtal1 xtal2 pll ( x 6.25) 48 mhz 2154_25.vsd psb 2154 usb module data sheet 76 2001-01-24 4.1 transfer modes usb data transfers take place between host and a particular endpoint on a usb device. a given usb device may support multiple data transfer endpoints. the usb host treats communications with any endpoint of a usb device independently from any other endpoint. such associations between the host software and a usb device endpoint are called pipes. as an example, a given usb device could have an endpoint supporting a pipe for transporting b1-channel data from the host to the usb device and another endpoint supporting a pipe for transporting b1-channel data from the usb device to the host. the usb architecture of the siuc-x comprehends all four basic types of data transfers, i.e. control, isochronous, interrupt and bulk. table 15 usb transfer modes mode function control control data are used to configure devices, data transmission is lossless. control pipes are bidirectional, data transfer is possible in both directions via one pipe. endpoint 0 is always configured as control endpoint with a maximum buffer length of 8 bytes. the control endpoint can be configured to handle data packets of 64 bytes maximum length. isochronous isochronous data are continuous and real-time in creation and consumption, such as voice data. in this case, real-time is defined from frame to frame. isochronous data transfer has the highest priority, but is not always lossless. isochronous pipes are always unidirectional, so one endpoint can be associated to an in pipe or an out pipe. the siuc-x supports up to 64 bytes. interrupt interrupt data are a small amount of data, which are transferred to the host every n frames, with n being programmable by the host. data delivery is lossless. interrupt pipes are always unidirectional in pipes, the maximum data packet length is limited to 64 bytes. bulk bulk data can be a larger amount of data, which can be split by the host in several data packets within one frame. data delivery is lossless. bulk pipes are always unidirectional, so one endpoint can be associated to an in pipe or an out pipe. the maximum data packet length is limited to 64 bytes. psb 2154 usb module data sheet 77 2001-01-24 4.2 memory buffer modes 4.2.1 overview every endpoint of the usb module can operate in 2 modes, dual buffer mode and single buffer mode. each mode provides random or sequential access to the usb memory. figure 25 shows the possible buffer modes. figure 25 memory buffer modes single buffer mode in single buffer mode, the usb and the cpu use one common memory page. the active buffer page is either page 0 or page 1. this mode is dedicated for data strings with a maximum length of 128 bytes. dual buffer mode in dual buffer mode the usb and the cpu write into different usb memory pages allowing back-to-back data transfers. switching between the pages is done automatically, enabling a high data transfer rate between the cpu and the usb module. this mode is dedicated for large data packets per frame (endless strings). random access random access is available in both modes. random access allows to change only a few bytes in a data block of the usb memory buffer without requiring the c to enter a complete data block. when the cpu has modified the bytes in the data block, setting of 2154_24.vsd buffer modes dual buffer mode single buffer mode random access sequential access random access sequential access psb 2154 usb module data sheet 78 2001-01-24 bit done by software marks the buffer ready for transmission or reception of data over the usb pipe. for modification of a specific byte in the buffer, the cpu must write the address to sfr adroff and read/write the data byte from/to register usbval. sequential access in sequential access mode the cpu accesses the data register usbval continuously without setting the address of the next usb memory buffer location. this is done automatically if bit ince (increment enable) in the related sfr epbcrn is set. after a specific number of cpu accesses (as done in sfr eplenn), the buffer has been read/ written by the cpu and is empty/full. setting of bit done in software, manually or automatically, marks the usb buffer ready. psb 2154 usb module data sheet 79 2001-01-24 4.2.2 single buffer mode in single buffer mode the usb and the cpu share one common usb memory page. the active buffer page can be either page 0 or page 1. back-to-back transfers are not possible in this mode. easy data storage and controlling can be achieved in this mode. e.g. a once created data set for an interrupt endpoint can be stored permanently in usb memory. as a result, an additional memory space for data storage is no longer needed. 4.2.2.1 usb write access figure 26 shows the basic flowchart of a usb write access to one usb memory buffer in single buffer mode. figure 26 usb write access in single buffer mode - buffer handling buffer is empty: usb write access enabled cpu read access disabled no cpu read access enabled usb write access disabled buffer is full: sod = 1 buffer full? buffer is written by usb no eod = 1 mcd03400 ye s ye s ye s usb write request? no buffer empty? buffer can be read by cpu psb 2154 usb module data sheet 80 2001-01-24 figure 27 shows more details of a usb write access to usb memory in single buffer mode. after sof(n) (start of frame) occured at , the usb starts writing at a fixed number of bytes into the usb memory. a byte counter is incremented after every usb memory write operation. when the usb memory write operation (len(n)) is finished correctly, bit sod (start of data) is set at , indicating a full usb memory buffer. furthermore, the byte counter value is stored in the corresponding length register, indicating the number of bytes which have been transferred and can be now read by the cpu. subsequently, the cpu can read data bytes from usb memory, generating an eod (end of data) at after the last byte has been read. bit eod set indicates an empty usb buffer, which now can be written again by the usb. figure 27 also shows a second usb write access operation with a different number of bytes (len(n+1)), where the cpu read operation from the usb memory is interrupted twice. figure 27 single buffer mode : standard usb write access note: the cpu accesses shown in the following diagrams assume that bit ince in the corres-ponding endpoint control register is set. a frame is the 1 ms time interval defined by the usb host. every frame begins with a sof token (start-of-frame). 1 2 3 4 1 eod set 4 frame n frame n+1 eod set time sof (n) set number of data bytes in usb buffer len (n) usb write accesses cpu read accesses mct03401 1 2 3 2 3 4 sod set set sod len (n+1) sof (n+2) set sof (n+1) set psb 2154 usb module data sheet 81 2001-01-24 4.2.2.2 usb read access figure 28 shows the basic flowchart of a usb read access from one usb memory buffer in single buffer mode. figure 28 usb read access in single buffer mode - buffer handling the standard usb read access as shown in figure 29 supports random and sequential cpu access mode of the usb memory. the memory buffer full condition is true when a predefined number of bytes (maxlen) has been written by the cpu or when bit done has been set by software. buffer is empty: usb read access disabled cpu write access enabled buffer can be written by cpu buffer full? no cpu write access disabled usb read access enabled buffer is full: eod = 1 usb read request? no buffer empty? buffer is read by usb no sod = 1 mcd03402 ye s ye s ye s psb 2154 usb module data sheet 82 2001-01-24 after sof(n) occured at with a full usb memory buffer, the usb reads the buffer. bit sod is set at the end of the usb buffer read operation at , indicating an empty usb memory buffer. now, the cpu can write again data into the usb memory buffer until a determined number (maxlen) of bytes are transfered or until bit done has been set by software. the maxlen value must be previously set by software. when the actual usb memory buffer address offset is equal to maxlen, bit eod is set at to indicate a full buffer. the usb memory buffer address offset is automatically incremented with every cpu write access to usb memory buffer if bit ince is set. during the next frame (after sof(n+1)) is set at ) the usb memory buffer can be read by the usb. bit sod is set again when the usb memory buffer becomes empty again. if bit done is set by the cpu (at ), the buffer is declared by the cpu to be full, even if the address offset does not reach the value of maxlen. figure 29 single buffer mode : standard usb read access the start-of-frame-done enable feature (sofde=1) is useful for usb memory read accesses when the number of data bytes to be transferred from cpu to usb is not predictable (see figure 30 ). the cpu can write data as desired to usb memory until a sof occures (every 1 ms). the automatic setting of bit sof causes bit eod to be set (at ). this indicates the cpu that no cpu action on this buffer is required until a usb read operation has been finished (bit sod set at ). setting of sod indicates an empty usb memory to the cpu which can start again writing data into usb memory. 1 2 3 4 5 1 eod set frame n frame n+1 done set time sof (n) set number of data bytes in usb buffer maxlen usb read accesses cpu write accesses mct03403 2 3 5 sod set sof (n+2) set set sof (n+1) 4 set sod 1 2 psb 2154 usb module data sheet 83 2001-01-24 figure 30 single buffer mode : usb read access with start-of-frame-done enabled 1 sod set 2 frame n frame n+1 sod set time sof (n) and eod set and eod sof (n+1) set number of data bytes in usb buffer maxlen usb read accesses cpu write accesses mct03404 psb 2154 usb module data sheet 84 2001-01-24 4.2.3 dual buffer mode in dual buffer mode, both usb memory pages (page 0 and page 1) are used for data transfers. the logical assignment of the memory pages to cpu or usb is automatically switched. the following two figures show the buffer handling concept in dual buffer mode for the usb read access and usb write access. figure 31 usb read access in dual buffer mode - buffer handling cpu buffer handling cpu page is empty : cbf = 0 cpu write access enabled cpu writes 1 byte cpu buffer full? cpu buffer is full : cbf = 1 cpu write access disabled pages are (cbf = 1 and ubf = 0) eod = 1 usb page empty? sod = 1 ye s ye s no no no ye s ye s full? cpu page usb read access disabled usb buffer is empty: ubf = 0 request? usb read usb reads buffer usb read access enabled usb page is full : ubf = 1 usb buffer handling no mcb03405 swapped psb 2154 usb module data sheet 85 2001-01-24 figure 32 usb write access in dual buffer mode - buffer handling figure 33 describes an example of a usb read operation in sequential mode with both buffers empty at the beginning of the usb read operation. the cpu starts writing data with sequential access (ince=1) to the buffer assigned to the cpu at . by definition, the buffer is full when maxlen is reached at . the second buffer assigned to the usb is empty (ubf=0) and as a result both buffers are logically swapped. now the buffer assigned to usb is full (ubf=1) and an usb read access can take place. after the usb read access, the buffer assigned to the usb is empty again with ubf=0. during the usb read access the cpu is still allowed to write into its assigned buffer. when reaching maxlen at , the cpu buffer is full and both buffers are again logically swapped. the usb further execute its read access. cpu buffer handling cpu page is full : cbf = 1 cpu read access enabled cpu reads 1 byte cpu buffer empty? cpu buffer is empty : cbf = 0 cpu read access disabled pages are (cbf = 0 and ubf =1) eod = 1 usb page full? sod = 1 ye s ye s no no no ye s ye s empty? cpu page usb write access disabled usb buffer is full: ubf = 1 request? usb write usb writes buffer usb write access enabled usb page is empty : ubf = 0 usb buffer handling no mcb03406 swapped 1 2 3 psb 2154 usb module data sheet 86 2001-01-24 figure 33 dual buffer mode usb read access: buffer switching when maxlen is reached in dual buffer mode, the physical assignment of the usb memory pages (page 0 or page 1) to either cpu buffer or usb buffer is controlled automatically in the usb module and cannot be selected by software. another way to initiate buffer switching is setting bit done by software. this feature, which is shown in figure 34 for usb read access, can be used to transfer a variable number of bytes. the maximum number of bytes to be transferred is still determined by maxlen, which is not changed when bit done is set. the actual packet length (len1 or len2) is the number of bytes which have been written to the buffer before bit done is set. frame n frame n+1 time sof (n) set number of data bytes maxlen usb read accesses cpu write accesses mct03407 sof (n+2) set time sof (n+1) set 1 3 page 0 page 1 page 1 page 0 ubf = 0 swap buffer swap buffer ubf = 0 usb buffer cpu buffer cbf = 0 maxlen page 0 2 page 1 ubf = 1 ubf = 1 psb 2154 usb module data sheet 87 2001-01-24 figure 34 dual buffer mode usb read access: buffer switching by setting bit done if bit sofde is set, buffer switching is done automatically after sof (start of frame) has been detected by the usb. figure 35 describes this functionality for usb read access for this case. the buffer which contains the latest data from the cpu is tagged valid for usb access (ubf=1) at and the buffers are swapped if the usb buffer is empty. after the usb read access has occured at , this buffer assigned to usb is empty again (ubf=0) and can be swapped again as soon as the cpu has filled its buffer (at ). the number of bytes in the buffer is less or equal maxlen. the maxlen threshold is always active, but an occurrence of sof (if sofde=1) or setting bit done by software are used to tag the cpu buffer full before reaching maxlen. frame n frame n+1 time sof (n) set number of data bytes maxlen usb read accesses cpu write accesses mct03408 done = 1 len1 sof (n+2) set time sof (n+1) set 1 3 page 0 page 1 page 1 page 0 ubf = 0 swap buffer swap buffer ubf = 0 usb buffer cpu buffer cbf = 0 len2 len1 maxlen len2 page 0 2 page 1 done = 1 ubf = 1 ubf = 1 1 2 3 psb 2154 usb module data sheet 88 2001-01-24 figure 35 dual buffer mode usb read access: buffer switching on sof with sofde=1 if the number of data bytes to be transferred is greater than the maximum packet size (given by maxlen), the data is split up automatically into packets, which are transferred one after the other. figure 36 gives an example of an usb read access, where data from the cpu is split up into two packets. when maxlen is reached during the cpu write access, the currently active buffer is switched to usb side (ubf=1). the cpu continues writing data to the buffer. when the complete data packet has been written to the buffer by the cpu, bit done is set by software to indicate the end of the data packet (cbf=1). in the example, the usb buffer has not been read out. it is still full for the usb and can not be swapped (cbf=ubf=1). when the usb read access has occured (cbf=0), the buffers are automatically swapped and bit sod is set. frame n frame n+1 time sof (n) set number of data bytes maxlen usb read accesses cpu write accesses mct03409 len1 sof (n+2) set time sof (n+1) set 2 1 3 page 0 page 1 page 1 page 0 ubf = 0 swap buffer swap buffer ubf = 0 usb buffer cpu buffer cbf = 0 len2 len1 maxlen len2 psb 2154 usb module data sheet 89 2001-01-24 figure 36 double buffer mode usb read access: data length greater than packet length (maxlen) frame n frame n+1 time sof (n) set number of data bytes maxlen usb read accesses cpu write accesses mct03410 sof (n+2) set time sof (n+1) set 1 page 1 page 1 swap buffer swap buffer ubf = 0 usb buffer cpu buffer cbf = 0 maxlen page 0 page 1 page 0 page 0 ubf = 1 ubf = 1 eod = 1 sod = 1 done = 1 cbf = 1 psb 2154 usb module data sheet 90 2001-01-24 in general, three criteria for buffer switching are implemented in the usb module: a) for sequential access, the address offset register adroff is automatically incremented after each read or write action of the cpu. the address offset value (before incrementing) represents the number of bytes stored in usb memory for a specific endpoint. if the address offset value (after incrementing) reaches the value stored in endpoint length register eplenn, the currently active buffer is tagged full (usb read access - all bytes have been written by cpu, cbf=1) or empty (usb write access - all bytes have been read by cpu, cbf=0). b) when bit done, which is located in the endpoint buffer status register epbsn, is set, software buffer switching is initiated. this action is independent from the number of bytes which have been handled by the cpu (possible in sequential access mode (ince=1) and random access mode (ince=0)). on cpu read accesses, the buffer is declared empty and bit cbf is cleared. if the buffer assigned to the usb is full (ubf=1), the buffers are immediately swapped. in this case, register eplenn contains the number of received bytes. on cpu write accesses, two different cases must be distinguished. for random accesses, the number of bytes of one packet is fixed by the value in register eplenn and does not change. for sequential accesses, the number of written bytes represents the packet size. in this case, the actual value of register adroff is transferred to register eplenn when bit done is set. c) the third criteria for buffer switching is the automatic buffer switching on detection of sof (see figure 36 ). this feature can be individually enabled (sofde=1) or disabled (sofde=0) by software selectively for each endpoint. 4.2.4 buffer underrun / overflow for the usb transfer modes control, interrupt and bulk, buffer underrun and buffer overflow conditions in the usb module are automatically handled by the udc using the usb specific low level control mechanism (ack, nak). for isochronous transfer no such control procedures are used. if a buffer underrun condition occurs at isochronous in transfers (c has failed to write data fast enough to the buffers), data packets with length "0" are transmitted to the host. in case of buffer overflow at isochronous out transfers (c has failed to read data fast enough from the buffers), new data packets received from the host will be discarded. psb 2154 usb module data sheet 91 2001-01-24 4.3 memory buffer organisation the address generation of the usb memory buffer is based on the address offset and base address pointer. this scheme allows flexible and application specific buffer allocation and management. the length of an endpoint buffer can be up to 8, 16, 32 or 64 bytes. the start address of each endpoint buffer can be located to memory locations according to table 16 . in order to avoid unused memory space between 2 endpoint buffers, the largest buffer should be located at the highest address. this structure should be used to allocate usb memory for all endpoint buffers. the base address for the setup packet is always located at address 00h. this leads to a typical usb buffer structure as shown in figure 37 . in this example, a buffer length of 8 bytes has been allocated to endpoints 0, 1, 2 and 7 while a buffer length of 16 bytes has been reserved for endpoints 3, 4, 5 and 6. the c allocates the usb memory buffers for all endpoints by programming the endpoint base address (epban) and the block size (eplen) within the total usb buffers. table 16 buffer length and base address values buffer length valid buffer base addresses 8 bytes 08 h , 10 h , 18 h , 20 h , 28 h , 30 h , 38 h , 40 h , 48 h , 50 h , 58 h , 60 h , 68 h , 70 h , 78 h 16 bytes 10 h , 20 h , 30 h , 40 h , 50 h , 60 h , 70 h 32 bytes 20 h , 40 h , 60 h 64 bytes 40 h psb 2154 usb module data sheet 92 2001-01-24 figure 37 endpoint buffer allocation (example: 7+1 endpoints) endpoint 6 buffer endpoint 5 buffer endpoint 4 buffer endpoint 3 buffer endpoint 7 buffer endpoint 2 buffer endpoint 1 buffer endpoint 0 buffer setup token 7f h 40 h 50 h 60 h 70 h 30 h 20 h 28 h 38 h 00 h 08 h buffer block epban eplenn endpoint 6 endpoint 5 endpoint 4 endpoint 3 endpoint 7 endpoint 2 endpoint 1 endpoint 0 setup token epba6=0e h epba5=0c h epba4=0a h epba3=08 h epba7=07 h epba2=06 h epba1=05 h epba0=04 h address 00 h on page 0 eplen6=10 h eplen5=10 h eplen4=10 h eplen3=10 h eplen7=08 h eplen2=08 h eplen1=08 h eplen0=08 h 8 bytes note: addroff = 00 h 2154_26.vsd psb 2154 usb module data sheet 93 2001-01-24 4.4 memory buffer address generation the generation of a usb memory address for usb access (read or write) depends on the epnum (endpoint number) information, which has been transmitted to the usb module during the software initialization procedure. the epnum information is used for the selection of an endpoint specific base address register. as the maximum data packet length of each endpoint can individually be programmed, there are some fixed start addresses for the endpoints. the user program defines the base address for the first data byte of the corresponding endpoint by writing the endpoint specific base address register epban. the length depends on the amount of data to be read or written. the user must take care to assign a buffer space at least as large as the maximum packet size of the endpoint. the address of the currently accessed byte in the usb memory area of the selected endpoint is defined by an address offset which must be added to the endpoint base address in order to get the correct address for the usb memory buffer. the structure is shown in figure 38 . figure 38 usb memory address generation epnum of the actual endpoint page0 0 0 0 a06 a05 a04 a03 epba0 page1 0 0 0 a16 a15 a14 a13 epba1 page2 0 0 0 a26 a25 a24 a23 epba2 page3 0 0 0 a36 a35 a34 a33 epba3 page4 0 0 0 a46 a45 a44 a43 epba4 page5 0 0 0 a56 a55 a54 a53 epba5 page6 0 0 0 a66 a65 a64 a63 epba6 page7 0 0 0 a76 a75 a74 a73 epba7 mux 0 an6 an5 an4 an3 pagex 0 0 epban 0 0 ao5 ao4 ao3 ao2 ao1 ao0 + adroff 0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 = usb mem addr usb memory page 0 page 1 an6 - an3 2154_27.vsd note: the epban and adroff registers should be programmed as required. the available memory is only 128 bytes, so some combinations do not make sense ! psb 2154 usb module data sheet 94 2001-01-24 4.5 usb initialization after a hardware reset operation, bit dcr.uclk is set to 0. a well defined procedure must be executed for switching on the clock for the usb module. this procedure is described in the operational description section. this switch-on procedure after a hardware reset assures proper operation of the usb clock system. the usb module must be functionally initialized from the c by writing five configuration bytes for each endpoint to the usbval register. table 17 shows the 5-byte configuration block which must be transmitted by the c to the usb module via the usbval register for each endpoint. the gray shaded fields have a fixed 0 or 1 value for each endpoint while the white bitfields have to be filled by parameters listed in table 18 . the five byte usb configuration block must be transferred sequentially (byte 0 to byte 4) from the c to the usb module for each endpoint beginning with endpoint 0, followed by the usb configuration block for endpoint 1 and so on up to the usb configuration block for endpoint 7. epnum is set to 000b, 001b,... up to 111b for endpoints 0 up to 7. after this action, bit dinit is reset by hardware and the software reset and initialization sequence is finished. this configuration can only be reset by a hardware or software reset (dcr.swr). a usb reset has no effect on the endpoint configuration, but will only reset the parameters address, configuration, interface and alternate setting to its default value 0. table 17 usb configuration block bit 39 bit 38 bit 37 bit 36 bit 35 bit 34 bit 33 bit 32 byte 0 0epnum 0 1 epinterface bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 byte 1 epaltsetting eptype epdir msb eppacksize bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 byte 2 eppacksize lsb 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 byte 3 0 0 0 0 0epnum bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 4 0 0 0 0 0 0 0 0 = constant data psb 2154 usb module data sheet 95 2001-01-24 table 18 bitfield definition of usb configuration block bitfield description epnum this 3-bit field specifies the number of the endpoint (0-7) for which the actual configuration byte block is valid. this 3-bit field must be entered in byte 0 and byte 3 of a configuration byte block epinterface this 2-bit field specifies the number of the interface (0-3) for which the configuration byte block is valid epaltsetting this 2-bit field selects the alternate setting of the corresponding interface (epinterface) for which the configuration byte block is valid. eptype this 2-bit field defines the transfer type of the endpoint 00: control endpoint 01: isochronous endpoint 10: bulk endpoint 11: interrupt endpoint endpoint 0 must be setup as a control endpoint epdir this byte defines the direction of the endpoint 0: out (packets to be transferred from host to cpu) 1: in (packets to be transferred from cpu to host) eppacksize this 10-bit field defines the maximum packet size to be transferred to this endpoint within the range from 0 up to 1023 bytes. the configuration of eppacksize must be in harmony with the usb specification. psb 2154 usb module data sheet 96 2001-01-24 4.6 usb device framework 4.6.1 enumeration process the bus enumeration process consists of an interrogation sequence through which the usb host acquires information from the connected device, gives it a unique address, and assigns it a configuration value. in the simplest form, the process takes four steps: step 1 : the host issues a get_descriptor command to the device through the default address using the control pipe. the device then provides information about itself, such as device class, vendor id, maximum packet size for endpoint 0, etc. step 2 : the host sends a unique address in a data packet to the device using the set_address command. the device, under software control, gets the address through endpoint 0 and stores it. step 3 : the host requests and reads the device configuration descriptor using the get_configuration command. the device responds with information about the number of interfaces and endpoints, endpoint transfer type, packet size and direction, maximum power requirements, power source, etc. step 4 : the last step of the enumeration process is handled using the set_configuration command through which the host assigns a configuration value to the device. after the enumeration process is complete, the device is configured and ready for usb data transmit and receive transactions. 4.6.2 control transfers a control transfer consists of at least two and perhaps three stages. this chapter gives a short description of these stages of a control transfer and the associated control and status bits. 4.6.2.1 setup stage a control transfer always begins with a setup stage that transfers information to a target device, defining the type of request being made to the usb device. the standard commands except the set_descriptor , get_descriptor and synch_frame commands are handled by the usb module automatically without cpu interaction. if the command is not handled by the usb module automatically, a setup interrupt (bit sui) indicates the end of a setup phase. additionally, the status and control bits ubf (usb buffer full), cbf (cpu buffer full) and sod (start of data) are reset. 4.6.2.2 data stage this stage occurs only for requests that require data transfers. the direction of this data stage is always predicted to be from host to device (bit epbsn.dirn is automatically cleared after the setup stage occurred). the first data packet may immediately be sent psb 2154 usb module data sheet 97 2001-01-24 from the host to the control endpoint according to this configuration of bit epbsn.dirn, while nack will automatically be returned from the device to the host in case of a usb read access. it also causes the direction bit to be changed (epbsn.dirn=1, usb read access). the direction of the next transfer can also be predicted under software control (bit epbsn.setrdn) to be a usb read access (epbsn.dirn=1). this feature is used, if the direction of the data stage is known and the data packet to be transferred from the cpu to the host is setup before the next usb access occurs. therefore, the direction bit must be changed under software control, to be able to transfer the data packet within the first usb read access. status bit sod is set under hardware control to indicate valid data to be read by the cpu in case of a usb write access, or data to be written by the cpu in case of a usb read access. 4.6.2.3 status stage the status stage always occurs to report the result of the requested operation. a status stage initiated by the host, but not terminated according to the configuration of epbsn.espn (espn=0) is indicated by a status interrupt (dirr.sti). bit epbsn.espn has to be set under software control to enable the acknowledge of the status stage. 4.6.3 standard device requests table 19 lists the standard requests possible. only the set_descriptor, get_descriptor and synch_frame requests require intervention from the cpu (dirr.sui interrupt). all other standard device requests are handled automatically by the udc and the cpu only gets a notification. since the device supports multiple device configurations, interfaces and alternate settings, a separate register ciar informs the cpu which configuration, interface and alternate setting is active. for further information please refer to the usb specification version 1.1, chapter 9.4 . table 19 standard device requests request description get_status this request returns status for the specified recipient, which can be a device, interface or endpoint. clear_feature this request is used to clear or disable a specific feature. the udc supports this command to clear the endpoint_stall feature for all supported logical endpoints and to clear the device_remote_ wakeup feature. psb 2154 usb module data sheet 98 2001-01-24 set_feature this request is used to set or enable a specific feature. the udc supports the set_feature command to set the endpoint_stall feature for all supported logical endpoints and the device_remote _wakeup feature. set_address this request sets the device address for all future device accesses. stages after the initial setup packet assume the same device address as the setup packet. the usb device does not change its device address until after the status stage of this request is completed successfully. this is the difference between this request and all other requests. for all other requests, the operation indicated must be completed before the status stage. get_descriptor * this request returns the specified descriptor if the descriptor exists. the standard request to a device supports three types of descriptors: device, configuration & string. a request for a configuration descriptor returns the configuration descriptor, all interface descriptors, and endpoint descriptors for all the interfaces in a single request. class-specific and/or vendor-specific descriptors follow the standard descriptors they extend or modify. this request must always be handled by the c. set_descriptor * this request may be used to update existing descriptors or add new descriptors. this request must always be handled by the c. get_configuration this request returns the current device configuration value. if the returned value is zero, the device is not configured. set_configuration this request sets the device configuration. get_interface this request returns the selected alternate setting for the specified interface. this is a valid request only when the device is in the configured state. table 19 standard device requests (cont ? d) request description psb 2154 usb module data sheet 99 2001-01-24 note: all 11 standard device requests generate an interrupt via the dsir register. the requests that always require host intervention are indicated with a " * " in the table above (get_descriptor, set_descriptor and sync-frame). all other 8 requests are automatically handled by the udc, but they are transparent to the c (the request get_status can be initialized by the c if required, the remaining 7 requests cannot be controlled by the c). set_interface this request allow the host to select an alternate setting for the specified interface. synch_frame * this request is used to set and then report an endpoint ? s synchronization frame. when an endpoint supports isochronous transfers, the endpoint may also require per-frame transfers to vary in size according to a specific pattern. the host and the endpoint must agree on which frame the repeating pattern begins. the number of the frame in which the pattern began is returned to the host. this frame number is the one conveyed to the endpoint by the last sof prior to the first frame of the pattern. the request sync_frame is used for isochronous endpoints only. this request must always be handled by the c. table 19 standard device requests (cont ? d) request description psb 2154 usb module data sheet 100 2001-01-24 4.7 onchip usb transceiver the siuc-x provides onchip receiver and transmitter circuitries which allows to connect the siuc-x directly to the usb bus. the usb driver circuitry is shown in figure 39 . the usb transceiver is capable of transmitting and receiving serial date at full speed (12 mbits/s) data rate. transceiver and receiver can be separately disabled for power down mode operation. a single ended zero error condition (d+ and d- both at low level) can be detected. figure 39 usb onchip driver circuitry the usb driver circuitry is a differential output driver which drives the usb data signal onto the cable of the usb bus. the static output swing of the transmitter is in low state below 0.3 v with a 1.5 k ? load to 3.6 v and in high state above 2.8 v with a 15 k ? load to v ss . the driver outputs support tri-state operation to achieve bi-directional half duplex operation (control bits rpwd and tpwd). high impedance is also required to isolate the port from devices that are connected but powered down. the driver tolerates exposure to waveforms as specified in chapter 7.1 of the usb v1.1 specification.. for a full speed usb connection the impedance of the usb driver must be between 29 ? and 44 ?. the data line rise and fall times are between 4 ns and 20 ns, smoothly rising or falling (monotonic), and are well matched to minimize rfi emissions and signal skew. figure 40 shows how the full speed driver is realized using two identical cmos buffers. figure 40 shows the full speed driver signal waveforms. d+ d- 1 0 tpwd dpwdr.1 + rpwd dpwdr.0 0 1 transmit data receive data pin pin 30 ? ? 30 mcs03413 psb 2154 usb module data sheet 101 2001-01-24 figure 40 full speed usb driver signal waveforms generally, full speed and low speed usb devices are differentiated by the position of the pullup resistor on the downstream end of the cable. full speed devices are terminated with the pullup on the d+ line and low speed devices are terminated with the pullup in the d- line. as the siuc is a full speed device an external pull-up resistor (r 2 ) must be connected to the d+ line as shown in figure 41 . the pullup terminator is a 1.5 k ? resistor tied to a voltage source between 3.0 and 3.6 v referenced to the local ground. in some cases it might be necessary to hide the usb device from the host even when it is plugged in. to accomplish this, the pull-up resistor r 2 can be made switchable with a port a transistor. figure 41 high speed device cable and resistor connection one bit time (12 mb/s) one-way trip cable delay v ss receiver signal pins signal pins driver signal pins pass input spec levels after one cable delay ss v se v max se v min mct03414 note: timings and voltage levels comply to the usb v1.1 spec fs / ls usb transceiver host or hub port d+ d- transceiver fs / ls usb d+ d- r 1 r 1 r 2 2 r full speed device twisted pair shielded 5 meters max. fs: full speed ls: low speed siuc psb 2154 usb module data sheet 102 2001-01-24 4.8 detach / attach detection and usb power modes the usb device can be used in two different modes concerning its power supply, the bus-powered mode and the self-powered mode. 4.8.1 self-powered mode in self-powered mode, the usb device has its own power supply. the usb device has to detect whether it is connected to usb bus or not. this detection is done by hardware by using the device-attached device-detached pin dadd as shown in figure 42 . bit dcr.da reflects the state of pin dadd. when the device-attached condition is detected, bit da is set and a device-attached interrupt (dirr.dai) can be generated if required. the interrupt service routine of this device interrupt must completely initialize the usb device/module. the device-detached detection resets bit da, sets bit dirr.ddi (device- detached interrupt) and can generate a device interrupt, too. figure 42 device attached - device detached detection in self-powered mode 4.8.2 bus-powered mode in bus-powered mode, the usb device is driven by the power supply from the usb bus. the maximum power consumption is given by the usb specification, i.e. the power consumption of the total system must not exceed 500 a in suspend mode and 100ma (for low power devices) in operational mode. an explicit device-attached detection in this mode is not necessary. if the cpu is running, the device is attached, so the usb device/module has to be configured only after power-on. the device-detach action has no significance concerning software, because the device is no longer powered and the cpu stops. as a result, no attach- detach detection is needed. in this mode, pin dadd can be used as standard io pin with bit da monitoring its status and the interrupt generation on da should not be used. if the interrupt generation on bit da remains activated, a request must not be interpreted as attached-detached action, but as an external interrupt request on pin dadd, which is generating a device interrupt. 2154_70 siuc-x v bus (+5v supply from usb) v ss gnd p3.1 / dadd 47 nf 100k 47k psb 2154 usb module data sheet 103 2001-01-24 4.9 usb registers two different kinds of registers are implemented in the usb module. 1.) the global registers describe the basic functionality of the complete usb module and can be accessed via unique sfr addresses. these are the: gepir (global endpoint interrupt request register) gesr (global endpoint stall register) epsel (endpoint select register) adroff (address offset register) usbval (usb value register) ciar (configuration request register) ciari (configuration request interrupt register) ciarie (configuration request interrupt enable register) ifcsel (interface select register) 2.) to reduce the number of sfr addresses needed to control the usb module, device registers and endpoint registers are mapped into an sfr address block of nine sfr addresses (c1 h to cc h ) for device and seven sfr addresses (c1 h to ca h ) for endpoint. the endpoint specific functionality of the usb module is controlled via the device registers: dcr (device control register) dpwdr (device power down register) dier (device interrupt enable register) dirr (device interrupt request register) fnrh, fnrl (frame number high/low registers) dsir (device setup interrupt register) dgsr (device get status register) igsr (interface get status register) an endpoint register set is available for each endpoint (n=0...7) and describes the functionality of the selected endpoint. figure 43 explains the structure of the usb module registers. note: in the description of the usb module registers, bits are marked as rw, r or w. bits marked as rw can be read and written. bits marked as r can be read only. writing any value to r bits has no effect. bits marked as w are used to execute internal commands which are triggered by writing a 1. writing a 0 to w bits has no effect. reading w bits returns a 0. psb 2154 usb module data sheet 104 2001-01-24 figure 43 usb register set 2154_28 .7 .6 .5 .4 .3 .2 .1 .0 gepir (d6 h ) 0 0 .5 .4 .3 .2 .1 .0 adroff (d4 h ) .7 .6 .5 .4 .3 .2 .1 .0 usbval (d3 h ) .7 0 0 0 .3 .2 .1 .0 epsel (d2 h ) fnrh fnrl dsir dirr dier dpwdr dcr c6 h c5 h c7 h c3 h c2 h c4 h c1 h device registers eplen0 epba0 epir0 epie0 epbs0 epbc0 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 0 registers eplen1 epba1 epir1 epie1 epbs1 epbc1 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 1 registers eplen2 epba2 epir2 epie2 epbs2 epbc2 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 2 registers eplen3 epba3 epir3 epie3 epbs3 epbc3 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 3 registers eplen4 epba4 epir4 epie4 epbs4 epbc4 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 4 registers eplen5 epba5 epir5 epie5 epbs5 epbc5 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 5 registers eplen7 epba7 epir7 epie7 epbs7 epbc7 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 7 registers eplen6 epba6 epir6 epie6 epbs6 epbc6 c6 h c5 h c3 h c2 h c4 h c1 h endpoint 6 registers decoder global registers igsr dgsr reserved cb h ca h cc h c8 h c9 h c7 h reserved c8 h c9 h egsr0 ca h c7 h reserved c8 h c9 h egsr1 ca h c7 h reserved c8 h c9 h egsr2 ca h c7 h reserved c8 h c9 h egsr3 ca h c7 h reserved c8 h c9 h egsr4 ca h c7 h reserved c8 h c9 h egsr5 ca h c7 h reserved c8 h c9 h egsr6 ca h c7 h reserved c8 h c9 h egsr7 ca h .7 .6 .5 .4 .3 .2 .1 .0 gesr (da h ) 0 0 0 0 0 0 .1 .0 ifcsel (db h ) psb 2154 usb module data sheet 105 2001-01-24 for each of the 4 interfaces (besides the default interface with endpoint 0) there is a 16- bit register that contains a status value which is transmitted to the usb host upon a get_status request ( figure 44 ). for setting the interface get status register (igsr) for a specific interface, the c first selects the interface number in the interface select register (ifcsel) and then writes the status value for the corresponding interface to igsr (note: igsr can only be accessed with epsel=80 h ). the status value itself (contained in igsr) is fully specified by the usb spec. there is no function defined for that yet in usb v1.1, however siuc fully supports the get_status request for potential changes in future. figure 44 usb interface get_status registers .7 0 0 0 .3 .2 .1 .0 epsel (d2 h ) fnrh fnrl dsir dirr dier dpwdr dcr c6 h c5 h c7 h c3 h c2 h c4 h c1 h device registers interface 0 registers interface 1 registers interface 2 registers interface 3 registers decoder global registers igsr dgsr reserved cb h ca h cc h c8 h c9 h cb h igsr cc h 0 0 0 0 0 0 .1 .0 ifcsel (db h ) cb h igsr cc h cb h igsr cc h cb h igsr cc h decoder c write access 2154_29 psb 2154 usb module data sheet 106 2001-01-24 global registers the global registers gepir, gesr, epsel, adroff, ifcsel and usbval describe the global functionality of the usb module and can be accessed via unique sfr addresses. the global endpoint interrupt request register (gepir) is described in the section on interrupts ( chapter 6 ), the other global registers are described below. standard command registers all 11 standard device requests generate an interrupt via the dsir register. the requests get_descriptor, set_descriptor and sync-frame always require host intervention. all other 8 requests are automatically handled by the udc, but they are transparent to the c (the request get_status can be initialized by the c if required, the remaining 7 requests cannot be controlled by the c at all). since the device supports multiple device configurations, interfaces and alternate settings, a separate register ciar is needed to inform the device which configuration, interface and alternate setting is active. any changes in the ciar register through set_configuration or set_interface will generate an interrupt in the configuration request interrupt register (ciari) . this interrupt can be enabled via a bit in the ciarie register. these registers are described in the section on interrupts ( chapter 6 ). device registers the device registers can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . the device interrupt enable register (dier), the device interrupt request register (dirr) and the device setup interrupt register (dsir) are described in the section on interrupts ( chapter 6 ), all other device registers are described below. endpoint registers each of the 8 endpoints has its own endpoint register set. the endpoint interrupt enable register (epie) and the endpoint interrupt request register (epir) are described in the section on interrupts ( chapter 6 ), all other endpoint registers are described below. psb 2154 usb module data sheet 107 2001-01-24 4.9.1 gesr- global endpoint stall register resetvalue:00 h address: da h the gesr register contains the least significant bits of the egsr registers of all 8 endpoints. 76543210 epst7 epst6 epst5 epst4 epst3 epst2 epst1 epst0 rrrrrrrr bit function epst7-0 endpoint x stalled epstx indicates to the c if the corresponding endpoint is stalled ( ? 1 ? ) or not ( ? 0 ? ). psb 2154 usb module data sheet 108 2001-01-24 4.9.2 epsel - endpoint select register resetvalue:80 h address: d2 h 76543210 eps70000eps2eps1eps0 rwrrrrrwrwrw bit function eps7 eps2 eps1 eps0 endpoint / device register block select bits these five bits select the active register block of endpoint or device registers. 1xxx: device register set selected 0000: endpoint 0 register set selected 0001: endpoint 1 register set selected 0010: endpoint 2 register set selected 0011: endpoint 3 register set selected 0100: endpoint 4 register set selected 0101: endpoint 5 register set selected 0110: endpoint 6 register set selected 0111: endpoint 7 register set selected psb 2154 usb module data sheet 109 2001-01-24 4.9.3 ifcsel - interface select register resetvalue:00 h address: db h also see figure 44 . 76543210 000000if1if0 rrrrrrrwrw bit function if1,0 interface select bits these two bits are used to select the interface number for setting the corresponding 16-bit status value in igsr. 00: interface 0 01: interface 1 10: interface 2 11: interface 3 psb 2154 usb module data sheet 110 2001-01-24 4.9.4 usbval - usb data register resetvalue:00 h address: d3 h the data transfers between usb memory and the c (c800 cpu) are handled via the sfr usbval. with a c write access to usbval, the value written into it is transferred to the usb memory location defined by the content of the endpoint specific base address register epban and the address offset register adroff. during usb memory read accesses by the c, data is written in the reverse direction. access to usbval is only successful if either epbsn.dirn=0 and cbf=1 (usb write operation) or epbsn.dirn=1 and cbf=0 (usb read operation). 76543210 .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw bit function usbval.7 - usbval.0 usb data value usbval stores the 8-bit data byte during transfers from c to usb memory and from usb memory to the c. bit nod in the epirn register indicates when the c processes a usbval read operation with an empty usb buffer or a usbval write operation to a full usb buffer. psb 2154 usb module data sheet 111 2001-01-24 4.9.5 adroff - address offset register resetvalue:00 h address: d4 h in most cases the c accesses only one endpoint buffer until it is full (cbf=1 during c write access) or empty (cbf=0 during c read access). as the usb memory size is 128 bytes per page, the maximum packet length is limited to 64 bytes. therefore, only the lowest 6 bits of adroff (ao5...ao0) are required for offset definition. a write operation to adroff is only successful if either epbsn.dirn=0 and cbf=1 (usb write operation) or epbsn.dirn=1 and cbf=0 (usb read operation). 76543210 0 0 ao5 ao4 ao3 ao2 ao1 ao0 r r rw rw rw rw rw rw bit function ao5 - ao0 usb address offset adroff stores the 6-bit offset address for usb memory buffer addressing by the c. psb 2154 usb module data sheet 112 2001-01-24 4.9.6 ciar - configuration request register resetvalue:00 h address: d9 h this register is used for the standard requests set_configuration and set_interface. 76543210 0 0 cfg 0 ifc1 ifc0 0 as r r r r r r r r bit function cfg configuration value 0: unconfigured 1: indicates configuration setting 1. ifc1-0 interface number ifc indicates the interface number for this configuration setting. a maximum of 4 interfaces (excluding interface 0) per configuration are possible. as alternate setting as indicates the selected alternate setting for that interface (ifc1-0). 0: alternate setting 0 1: alternate setting 1 psb 2154 usb module data sheet 113 2001-01-24 4.9.7 dcr - device control register the device control register includes control and status bits which indicate the current status of the usb module and the status of the usb bus. this register can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . reset value: 000x0000 b address: c1 h 76543210 0 da swr susp dinit rsm uclk 0 rrrwrrrwrwr bit function da device attached bit da reflects the state of pin dadd, which can be used to indicate whether the device is attached to the usb bus or not in self-powered mode. if pin dadd is 0, bit da=0. if pin dadd is 1, bit da=1. if the "device-attached/device-detached" feature is not required (e.g. in bus-powere mode), pin dadd and bit da can be used as general purpose input (for further information see chapter 4.8 ). swr software reset setting bit swr initiates a software reset operation of the usb device. this bit is cleared by hardware after a successful reset operation. swr can not be reset by software. susp suspend mode this bit is set when the usb is idle for more than 3 ms. it will remain set until there is a non idle state on the usb cable or when bit rsm is set. in addition to susp an interrupt can be generated when the suspend mode begins (dirr.sbi) and when it ends (dirr.sei) dinit device initialization in progress at the end of a software reset, bit dinit is set by hardware. after software reset of the usb module, it must be initialized by the cpu. when dinit is set after a software reset, 5 bytes for each endpoint must be written to sfr usbval. after the 40th byte, bit done0 has to be set by software. bit dinit is reset by software after a successful initialization sequence. psb 2154 usb module data sheet 114 2001-01-24 rsm resume bus activity when the usb device is in suspend mode, setting bit rsm resumes bus activity. in response to this action, the usb will deassert the suspend bit and perform the remote wake-up operation. writing 0 to rsm has no effect, the bit is reset if bit susp is 0. uclk udc clock selection bit uclk controls the functionality of the usb core clock. if uclk=0, the 48 mhz usb core clock is disabled. if uclk=1, the 48 mhz usb core clock is enabled. psb 2154 usb module data sheet 115 2001-01-24 4.9.8 dpwdr - device power down register the device power down register (dpwdr) includes 2 bits which allow to switch off the usb transmitter and receiver circuitry selectively for power down mode operation. this register can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . resetvalue:00 h address: c2 h 76543210 000000tpwdrpwd rrrrrrrwrw bit function tpwd usb transmitter power down setting bit tpwd puts the usb transmitter into power down mode. after a wake-up from software power down mode, bit tpwd must be cleared by software to enable data transmission again. rpwd usb receiver power down setting bit rpwd puts the usb receiver into power down mode. after a wake-up from software power down mode, bit rpwd must be cleared by software to enable data reception again. note: if rpwd is set, the usb bus can not wake-up the device from power down mode. psb 2154 usb module data sheet 116 2001-01-24 4.9.9 fnrh / fnrl - frame number register high / low byte the frame number registers store an 11-bit value which defines the number of a usb frame. the frame number rolls over upon reaching its maximum value of 7ff h . the fnrh/fnrl registers are read only registers which are reset to 00 h by a hardware reset. these registers can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . reset value: 00000xxx b address: c7 h resetvalue:xx h address: c6 h 76543210 fnrh 00000fnr10fnr9fnr8 rrrrrrrr 76543210 fnrl fnr7 fnr6 fnr5 fnr4 fnr3 fnr2 fnr1 fnr0 rrrrrrrr bit function fnr10 - fnr0 frame number value fnr10-8 and fnr7-0 hold the current 11-bit frame number of the latest sof token. psb 2154 usb module data sheet 117 2001-01-24 4.9.10 dgsr - device get_status register these two registers hold a 16-bit value that is sent to the usb host upon a "device get status" command. these registers can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . resetvalue:00 b address: ca h resetvalue:00 h address: c9 h the function of this register is completely determined by the usb specification. for further functional additions the higher bits of this register (dst15-2) can be programmed to "1" to fulfill future requirements. 76543210 dst15 dst14 dst13 dst12 dst11 dst10 dst9 dst8 rw rw rw rw rw rw rw rw 76543210 dst7 dst6 dst5 dst4 dst3 dst2 rwup pstat rw rw rw rw rw rw r rw bit function rwup remote wakeup (set/cleared by the usb host) the remote wakeup status is configured by the host using the set_feature_remote_wakeup and the status is returned to the host with every get_status request. 0: remote wakeup disabled 1: remote wakeup enabled this bit cannot be written by the c. pstat usb power status this bit indicates to the host whether the usb device is operating in bus- powered mode ("0") or in self-powered mode ("1"). this bit has no effect on the functions of the device. psb 2154 usb module data sheet 118 2001-01-24 4.9.11 igsr - interface get_status register these two registers hold a 16-bit value that is sent to the usb host upon an "interface get status" command. these registers can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . the interface number (0...3) is selected in ifcsel. resetvalue:00 b address: cc h resetvalue:00 h address: cb h the function of this register is completely determined by the usb specification. for further functional additions the bits of this register (ist15-0) can be programmed to "1" to fulfill future requirements. also see figure 44 . 76543210 ist15 ist14 ist13 ist12 ist11 ist10 ist9 ist8 rw rw rw rw rw rw rw rw 76543210 ist7 ist6 ist5 ist4 ist3 ist2 ist1 ist0 rw rw rw rw rw rw rw rw psb 2154 usb module data sheet 119 2001-01-24 4.9.12 epbcn - endpoint buffer control register the endpoint buffer control register controls the endpoint specific operations. the index n corresponds to the selected endpoint. resetvalue:00 h address: c1 h 7654 3210 stalln 0 0 gepien sofden incen 0 dbmn rw r r rw rw rw r rw bit function stalln endpoint stall bit stall can be set to indicate that the endpoint is stalled. if the stall bit for endpoint 0 (stall0) is set, the next incoming setup token will automatically clear it. if stall=0, the endpoint n is active if stall=1, the endpoint n is stalled gepien global endpoint interrupt enable bit gepien enables or disables the generation of the global endpoint interrupt n based on the endpoint specific interrupt request bits in register epirn. if gepie=0, the usb endpoint n interrupt is disabled if gepie=1, the usb endpoint n interrupt is enabled sofden start of frame done enable if bit sofde is set, the current cpu buffer in usb memory is automatically tagged full (data flow from the cpu to usb) or empty (data flow from usb to the cpu) on each detection of a start of frame on the usb (auto-done). if sofde=0, no action takes place on sof if sofde=1, automatic generation of done on sof is enabled psb 2154 usb module data sheet 120 2001-01-24 4.9.13 epbsn - endpoint buffer status register the bits of the endpoint buffer status registers indicate the status of the endpoint specific usb memory buffers and allows setting of certain usb memory buffer conditions. resetvalue:20 h address: c2 h incen auto increment enable if bit ince is set, the address offset register adroff for cpu access to usb memory is automatically incremented after each data write or data read action of the usbval register. this allows the user to handle the usb memory like a fifo without modification of the address of the desired memory location by software. dbmn dual buffer mode bit dbm allows the selection between single buffer mode and dual buffer mode. if dbm=0, single buffer mode is selected if dbm=1, dual buffer mode is selected 76543 2 10 ubfn cbfn dirn espn setrdn setwrn clrepn donen r r r w w w w w bit function ubfn usb buffer full bit ubfn indicates the status of the usb memory buffer for endpoint n. usb read access: if ubfn=0, the usb buffer for endpoint n is empty. if ubfn=1, the usb buffer for endpoint n is not empty. usb write access: if ubfn=0, the usb buffer for endpoint n is not full. if ubfn=1, the usb buffer for endpoint n is full. psb 2154 usb module data sheet 121 2001-01-24 cbfn cpu buffer full bit cbfn indicates the status of the cpu memory buffer for endpoint n. cpu read access: if cbfn=0, the cpu buffer for endpoint n is empty. if cbfn=1, the cpu buffer for endpoint n is not empty. cpu write access: if cbfn=0, the cpu buffer for endpoint n is not full. if cbfn=1, the cpu buffer for endpoint n is full. dirn direction of usb memory access bit dirn indicates the direction of the last usb memory access for endpoint n. if dirn=0, the last data flow for endpoint n was from host to cpu if dirn=1, the last data flow for endpoint n was from cpu to host espn enable status phase if bit espn is set, the next status phase of endpoint n will automatically be acknowledged by an ack except if the endpoint n is stalled. if the status phase is successfully completed, bit espn is automatically reset by hardware and no status interrupt request (dirr.sti) is generated. if the cpu detects a corrupted control transfer (endpoint 0), bit stall0 should be set by software instead of bit esp0 in order to indicate an error condition from which the usb device can not recover by itself. setrdn set direction of usb memory buffer to read bit setrdn is used to predict the direction of the next usb access for endpoint n as a usb read access. a faulty prediction causes no errors since the usb module determines the real direction. a change in the data direction is only executed if both usb memory buffers are empty. setrdn can not be set together with clrepn because a change of bit dirn during a transfer is not allowed. note: bits setrdn and setwrn must not be set at the same time. setwrn set direction of usb memory buffer to write bit setwrn is used to predict the direction of the next usb access for endpoint n as a usb write access. a faulty prediction causes no errors since the usb module determines the real direction. a change in the data direction is only executed if both usb memory buffers are empty. setwr can not be set together with clrepn because a change of epbsn.dirn during a transfer is not allowed. note: bits setwrn and setrdn must not be set at the same time. psb 2154 usb module data sheet 122 2001-01-24 4.9.14 epban - endpoint base address register the endpoint base address and length registers define the location and size (start address and length) of the endpoint specific buffers in the usb memory (also see chapter 4.9.15 ). resetvalue:00 h address: c5 h clrepn clear endpoint setting bit clrepn will set the address offset register for a cpu access to usb memory to 0. the bits cbfn and ubfn will be reset when clrepn is set. bit clrepn is reset by hardware. a read operation of this bit will always deliver 0. setting of bit clrepn does not change the direction of endpoint n. this means, bit dirn is not changed. note: when bits clrepn and espn are set simultaneously with one instruction, bit espn remains set and the next status phase is enabled. if only clrepn is set, bit espn is reset and the status phase is disabled. setting bits clrepn and setrdn or setwrn simultaneously with one instruction is not allowed. this means that the setting of setrdn or setwrn is ignored. donen buffer done by cpu if bit done is set, the current usb memory buffer assigned to cpu is automatically tagged full (data flow from the cpu to usb) or empty (data flow from usb to the cpu). this bit is reset by hardware after it has been set. a read operation of this bit always delivers a 0. note: if the direction of the endpoint is read (usb read access) and auto- increment is enabled (incen=1) and donen is set, the content of register adroff is copied automatically to register eplenn of the actual endpoint. register eplenn is not changed if the auto-increment capability is disabled (incen=0). 76543 2 10 pagen 0 0 0 an6 an5 an4 an3 r r r r rw rw rw rw psb 2154 usb module data sheet 123 2001-01-24 4.9.15 eplenn - endpoint buffer length register reset value: 0xxxxxxx b address: c6 h bit function pagen buffer page for endpoint n (single buffer mode only) in single buffer mode, the endpoint n can be either located on usb memory buffer page 0 (pagen=0) or on usb memory buffer page 1 (pagen=1) by clearing or setting this bit. in dual buffer mode this bit has no effect. note: the setup token is always stored on usb memory buffer page 0 at address 00 h to 07 h . an6-an3 endpoint n buffer start address the bits 0 to 3 of epban are the address bits a6 to a3 of the usb memory buffer start address for endpoint n. a7 and a2-a0 of the resulting usb memory buffer start address are set to 0. 76543 2 10 0 ln6 ln5 ln4 ln3 ln2 ln1 ln0 r rw rw rw rw rw rw rw bit function ln6 - ln0 endpoint n buffer length the bits 0 to 6 of eplenn define the length of the usb memory buffer for endpoint n and can not be written if dinit=1. psb 2154 usb module data sheet 124 2001-01-24 4.9.16 egsr - endpoint get_status register these two registers hold a 16-bit value that is sent to the usb host upon an "endpoint get status" command. resetvalue:00 b address: ca h resetvalue:00 h address: c9 h the function of this register is completely determined by the usb specification. for further functional additions the higher bits of this register (est15-1) can be programmed to "1" to fulfill future requirements. 76543210 est15 est14 est13 est12 est11 est10 est9 est8 rw rw rw rw rw rw rw rw 76543210 est7 est6 est5 est4 est3 est2 est1 stall rw rw rw rw rw rw rw r bit function stall endpoint stalled (set/cleared by the usb host) the endpoint stall status can be read by the c in the gesr register and the status is returned with every get_status request for endpoint. 0: endpoint is not stalled 1: endpoint is stalled this bit cannot be written by the c. psb 2154 isdn module data sheet 125 2001-01-24 5isdn module 5.1 general functions and architecture figure 45 shows the architecture of the isdn block containing the following functions: s/t-interface transceiver operating in terminal mode (te) serial or parallel microcontroller interface two b-channel hdlc-controller with 128 byte flfos per channel and per direction with programmable fifo block size (threshold) one d-channel hdlc-controller with 64 byte flfos per direction with programmable fifo block size (threshold) iom-2 interface for terminal applications (te mode) d-channel access mechanism c/i- and monitor channel handler auxiliary interface with interrupt and general purpose i/o lines and led drivers clock and timing generation digital pll to synchronize the transceiver to the s/t interface reset generation (watchdog timer) spi interface for connection of a serial eeprom the functional blocks are described in the following chapters. figure 45 functional block diagram of the siuc-x note: all addresses mentioned in the isdn chapter must be prefixed by f8 h to correspond to the isdn address space f800 h - f8ff h (see chapter 5.8 ). reset, interrupt generation iom-2 interface iom-2 handler b-channel hdlc rx/tx fifos b-channel hdlc rx/tx fifos d-channel hdlc rx/tx fifos auxiliary interface s transceiver c/i tic mon handler osc dpll microcontroller access peripheral devices i/o-lines and spi interface 2154_56.vsd isdn registers s psb 2154 isdn module data sheet 126 2001-01-24 5.1.1 timer 2 and 3 the siuc provides 4 timers (timer 0, 1, 2 and 3). timer 0 and timer 1 are located in the microcontroller module (see chapter 3.5 ), timer 2 and 3 are embedded in the isdn module and described below. each of both timers provide two modes ( table 20 ), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. when the programmed period has expired an interrupt is generated and indicated in the auxiliary interrupt status ista.aux (enabled/disabled via ien2.aux). the source of the interrupt can be read from auxi (tin2, tin3) and each of the interrupt sources can individually be masked in auxm. figure 46 timer 1 and 2 interrupt status registers table 20 siuc-x timers address register modes period 24 h timr2 periodic 64 ... 2048 ms count down 64 ms ... 14.336 s 65 h timr3 periodic 1 ... 63 ms count down 1 ... 63 ms st icb mos tran icd cic aux interrupt ista ien2 aux ica wov tin3 tin2 wov tin3 tin2 auxm auxi int1 int0 int1 int0 eaw eaw psb 2154 isdn module data sheet 127 2001-01-24 timer 2 the host controls the timer 2 by setting bit cmdrd.sti to start the timer and by writing register timr2 to stop the timer. after time period t1 an interrupt (auxi.tin2) is generated continuously if cnt=7 or a single interrupt is generated after timer period t if cnt<7 ( figure 47 ). figure 47 timer 2 register timer 3 the host starts and stops timer 3 in timr3.cnt ( figure 48 ). if timr3.tmd=0 the timer is operating in count down mode, for timr3.tmd=1 a periodic interrupt auxi.tin3 is generated. the timer length (for count down timer) or the timer period (for periodic timer), respectively, can be configured to a value between 1 - 63 ms (timr3.cnt). figure 48 timer 3 register further timers are available in the microcontroller module (see chapter 3.5 ). 2154_19 cnt value 76543210 24 h expiration period t1 = (value + 1) x 0.064 sec retry counter 0 ... 6 : count down timer t = cnt x 2.048 sec + t1 7 : periodic timer t = t1 timr2 2154_19 cnt 76543210 65 h timer count 0: timeroff 1 ... 63 : 1 ... 63 ms timer mode 0 : count down timer 1 : periodic timer timr3 tmd 0 psb 2154 isdn module data sheet 128 2001-01-24 5.1.2 activation indication via pin acl the activated state of the s-interface is directly indicated via pin acl (activation led). an led with pre-resistance may directly be connected to this pin and a low level is driven on acl as soon as the layer 1 state machine reaches the activated state (see figure 49 ). figure 49 acl indication of activated layer 1 by default (acfg2.acl=0) the state of layer 1 is indicated at pin acl . if the automatic indication of the activated layer 1 is not required, the state on pin acl can also be controlled by the host (see figure 50 ). if acfg2.acl=1 the led on pin acl can be switched on (acfg2.led=1) and off (acfg2.led=0) by the host. figure 50 acl configuration 2154_57.vsd layer 1 acfg2:led 0: off 1: on acfg2:acl '1' '0' acl +3.3v s interface psb 2154 isdn module data sheet 129 2001-01-24 5.2 s/t-interface the layer-1 functions for the s/t interface of the siuc-x are: ? line transceiver functions for the s/t interface according to the electrical specifications of itu-t i.430; ? conversion of the frame structure between iom-2 and s/t interface; ? conversion from/to binary to/from pseudo-ternary code; ? level detection ? receive timing recovery for point-to-point, passive bus and extended passive bus configuration ? s/t timing generation using iom-2 timing synchronous to system, or vice versa; ? d-channel access control and priority handling; ? d-channel echo bit generation by handling of the global echo bit; ? activation/deactivation procedures, triggered by primitives received over the iom-2 c/i channel or by info's received from the line; ? execution of test loops. the wiring configurations in user premises, in which the siuc-x can be used, are illustrated in figure 51 . psb 2154 isdn module data sheet 130 2001-01-24 figure 51 wiring configurations in user premises 2154_58.vsd siuc-x isac-sx tr te tr lt-s 1000 m 1) point-to-point configurations isac-sx tr tr nt / lt-s 100 m siuc-x isac-sx tr te1 tr nt / lt-s 10 m extended passive bus siuc-x te8 25 m 500 m .... siuc-x te1 10 m siuc-x te8 .... short passive bus tr: terminating resistor 1) the maximum line attenuation tolerated by the siuc-x is 7 db at 96 khz. psb 2154 isdn module data sheet 131 2001-01-24 5.2.1 s/t-interface coding transmission over the s/t-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (b1+b2+d), 48 kbit/s are used for framing and maintenance information. line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. figure 52 s/t -interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 53 ). in the direction te nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits. 011 code violation psb 2154 isdn module data sheet 132 2001-01-24 figure 53 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. ? f framing bit f = (0b) identifies new frame (always positive pulse, always code violation) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d received e-bit is equal to transmitted d-bit ? f a auxiliary framing bit see section 6.3 in itu i.430 ? nn = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 channel data (see note below) ? m multiframing bit m = (1b) start of new multiframe f a psb 2154 isdn module data sheet 133 2001-01-24 5.2.2 s/t-interface multiframing according to itu recommendation i.430 a multiframe provides extra layer 1 capacity in the te-to-nt direction by using an extra channel between the te and nt (q-channel). the q bits are defined to be the bits in the f a bit position. in the nt-to-te direction the s-channel bits are used for information transmission. one s channel (s1) out of five possible s-channels can be accessed by the siuc-x. the s and q channels are accessed via the c interface or the iom-2 monitor channel, respectively, by reading/writing the sqr or sqx bits in the s/q channel registers (sqrrx, sqxrx). table 21 shows the s and q bit positions within the multiframe. table 21 s/q-bit position identification and multiframe structure after multiframe synchronization has been established, the q data will be inserted at the upstream (te nt) f a bit position in each 5th s/t frame (see table 21 ). frame number nt-to-te f a bit position nt-to-te m bit nt-to-te s bit te-to-nt f a bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s11 s21 s31 s41 s51 q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s12 s22 s32 s42 s52 q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s13 s23 s33 s43 s53 q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s14 s24 s34 s44 s54 q4 zero zero zero zero 1 2 one zero one zero s11 s21 q1 zero psb 2154 isdn module data sheet 134 2001-01-24 when synchronization is not achieved or lost, each received f a bit is mirrored to the next transmitted f a bit. multiframe synchronization is achieved after two complete multiframes have been detected with reference to f a /n bit and m bit positions. multiframe synchronization is lost if bit errors in f a /n bit or m bit positions have been detected in two consecutive multiframes. the synchronization state is indicated by the msyn bit in the s/q-channel receive register (sqrr1). the multiframe synchronization can be enabled or disabled by programming the mfen bit in the s/q-channel transmit register (sqxr1). if enabled (tr_conf1.en_sfsc=1) the first frame within a multiframe generates a short fsc, i.e. every 40th iom-frame a short fsc is generated. interrupt handling for multiframing to trigger the microcontroller for a multiframe access an interrupt can be generated once per multiframe (sqw) or if the received s-channels have changed (sqc). in both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms). psb 2154 isdn module data sheet 135 2001-01-24 5.2.3 multiframe synchronization (m-bit) the siuc-x offers the capability to control the start of the multiframe from external signals, so applications which require synchronization between different s-interfaces are possible. such an application is the connection of dect base stations to pbx line cards. for this purpose a multiplexed function of the aux4 pin is used. if the acfg2.a4sel is set to ? 1 ? the pin is not used as general pupose i/o pin but as m-bit output. figure 54 multiframe synchronization using the m-bit in te mode the siuc-x outputs the value of the m-bit on the mbit pin. the value of m should be sampled at the falling edge of fsc. frame relationship figure 55 frame relationship in te mode (m-bit output) 2154_64 s-transceiver (lt-s, nt) s-transceiver (te, lt-t) mbit s-interface mbit m-bit input m-bit output fsc short fsc output fsc short fsc input 21150_30 s(nt->te) dd (o) fsc b1 b1 b2 b2 f d d d m e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 d m i-1 m mbit (o) psb 2154 isdn module data sheet 136 2001-01-24 5.2.4 data transfer and delay between iom-2 and s/t in the state f7 (activated) or if the internal layer-1 statemachine is disabled and xinf of register tr_cmd is programmed to ? 011 ? the b1, b2, d and e bits are transferred transparently from the s/t to the iom-2 interface. in all other states ? 1 ? s are transmitted to the iom-2 interface. to transfer data transparently to the s/t interface any activation request c/i command (ar8, ar10 or arl) is additionally necessary or if the internal layer-1 statemachine is disabled, bit tddis of register tr_cmd has additionally to be programmed to ? 0 ? . figure 56 shows the data delay between the iom-2 and the s/t interface and vice versa. for the d channel the delay from the iom-2 to the s/t interface is only valid if s/g evaluation is disabled (moded:dim0=0). if s/g evaluation is enabled (moded.dim2-0=0x1 b ) the delay depends on the selected priority and the relation between the echo bits on s and the d channel bits on the iom-2, e.g. for priority 8 the timing relation between the 8th d-bit on s bus and the d-channel on iom-2. figure 56 data delay between iom-2 and s/t interface (te mode) line_iom_s.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 psb 2154 isdn module data sheet 137 2001-01-24 figure 57 data delay between iom-2 and s/t interface with s/g bit evaluation (te mode) line_iom_s_dch.vsd nt -> te dd du fsc te -> nt b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d b1 b1 b2 b2 f d d d d e e e e b1 b1 b2 b2 f d d d d e e e e e e e e b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 b2 d b1 mapping of b-channel timeslots 1. possibility 2. possibility mapping of a 4-bit group of d-bits on s and iom depends on prehistory (e.g. priority control): psb 2154 isdn module data sheet 138 2001-01-24 5.2.5 transmitter characteristics the full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source (v sx1/sx2 = +/-1.05v; i max = 26 ma). the equivalent circuit of the transmitter is shown in figure 58 . the nominal pulse amplitude on the s-interface 750 mv (zero-peak) is adjusted with external resistors (see chapter 5.2.7.1 ). figure 58 equivalent internal circuit of the transmitter stage 21150_28 level '+0' '-0' '1' '+0' '-0' '1' vcm+0.525v vcm-0.525v vcm vcm-0.525v vcm+0.525v vcm tr_conf2.dis_tx '+0' '1' '-0' + - v=1 vcm - + v=1 sx2 sx1 psb 2154 isdn module data sheet 139 2001-01-24 5.2.6 receiver characteristics the receiver consists of a differential input stage, a peak detector and a set of comparators. additional noise immunity is achieved by digital oversampling after the comparators. a simplified equivalent circuit of the receiver is shown in figure 59 . figure 59 equivalent internal circuit of the receiver stage the input stage works together with external 10 k ? resistors to match the input voltage to the internal thresholds. the data detection threshold vref is continiously adapted between a maximal (vrefmax) and a minimal (vrefmin) reference level related to the line level. the peak detector requires maximum 2 s to reach the peak value while storing the peak level for at least 250 s (rc > 1 ms). the additional level detector for power up/down control works with a fixed threshold vrefld. the level detector monitors the line input signals to detect whether an info is present. when closing an analog loop it is therefore possible to indicate an incoming signal during activated loop. 100 kohm psb 2154 isdn module data sheet 140 2001-01-24 5.2.7 s/t interface circuitry for both, receive and transmit direction a 1:1 transformer is used to connect the siuc- x transceiver to the 4 wire s/t interface. typical transformer characteristics can be found in the chapter on electrical characteristics. the connections of the line transformers is shown in figure 60 . figure 60 connection of line transformers and power supply to the siuc-x for the transmit direction an external transformer is required to provide isolation and pulse shape according to the itu-t recommendations. 5.2.7.1 external protection circuitry the itu-t i.430 specification for both transmitter and receiver impedances in tes results in a conflict with respect to external s-protection circuitry requirements: ? to avoid destruction or malfunction of the s-device it is desirable to drain off even small overvoltages reliably. ? to meet the 96 khz impedance test specified for transmitters and receivers (for tes only, itu-t i.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be dimensioned such that voltages below 1.2 v (itu-t i.430 amplitude) x transformer ratio are not affected. this requirement results from the fact that this test is also to be performed with no supply voltage being connected to the te. therefore the second reference point for overvoltages v dd , is tied to gnd. then, if the amplitude of the 96 khz test signal is greater than the combined forward voltages of the diodes, a current exceeding the specified one may pass the protection circuit. the following recommendations aim at achieving the highest possible device protection against overvoltages while still fulfilling the 96 khz impedance tests. 2154_59.vsd siuc-x protection circuit protection circuit 1:1 1:1 transmit pair receive pair sx1 sx2 sr1 sr2 psb 2154 isdn module data sheet 141 2001-01-24 protection circuit for transmitter figure 61 external circuitry for transmitter figure 61 illustrates the secondary protection circuit recommended for the transmitter. the external resistors (r = 5 ... 10 ? ) are required in order to adjust the output voltage to the pulse mask on the one hand and in order to meet the output impedance of minimum 20 ? (transmission of a binary zero according to itu-t i.430) on the other hand. two mutually reversed diode paths protect the device against positive or negative overvoltages on both lines. an ideal protection circuit should limit the voltage at the sx pins from ? 0.4 v to v dd + 0.4 v. with the circuit in figure 61 the pin voltage range is increased from ? 1.4 v to v dd + 0.7 v. the resulting forward voltage of 1.4 v will prevent the protection circuit from becoming active if the 96 khz test signal is applied while no supply voltage is present. protection circuit for receiver figure 62 illustrates the external circuitry used in combination with a symmetrical receiver. protection of symmetrical receivers is rather simple. figure 62 external circuitry for symmetrical receivers sx1 vdd sbus 1:1 3081_23 sx2 r r note: up to 10 pf capacitors are optional for noise reduction 1:1 s bus psb 2154 isdn module data sheet 142 2001-01-24 between each receive line and the transformer a 10 k ? resistor is used. this value is split into two resistors: one between transformer and protection diodes for current limiting during the 96 khz test, and the second one between input pin and protection diodes to limit the maximum input current of the chip. with symmetrical receivers no difficulties regarding lcl measurements are observed; compensation networks thus are obsolete. in order to comply to the physical requirements of itu-t recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the siuc-x may need additional circuitry. 5.2.8 s/t interface delay compensation the s/t transmitter is shifted by two s/t bits minus 7 oscillator periods (plus analog delay plus delay of the external circuitry) with respect to the received frame. to compensate additional delay introduced into the receive and transmit path by the external circuit the delay of the transmit data can be reduced by another two oscillator periods (2 x 130 ns). therefore pds of the tr_conf2 register must be programmed to ? 1 ? . this delay compensation might be necessary in order to comply with the "total phase deviation input to output" requirement of itu-t recommendation i.430 which specifies a phase deviation in the range of ? 7% to + 15% of a bit period. 5.2.9 level detection power down if mode1.cfs is set to ? 0 ? , the clocks are also provided in power down state, whereas if cfs is set to ? 1 ? only the analog level detector is active in power down state. all clocks, including the iom-2 interface, are stopped (dd, du are ? high ? , dcl and bcl are ? low ? ). an activation initiated from the exchange side will have the consequence that a clock signal is provided automatically if tr_conf0.ldd is set to ? 0 ? . if tr_conf0.ldd is set to ? 1 ? the microcontroller has to take care of an interrupt caused by the level detect circuit (istatr.ld) from the terminal side an activation must be started by setting and resetting the spu- bit in the iom_cr register and writing tim to the cix0 register or by resetting mode1.cfs=0. psb 2154 isdn module data sheet 143 2001-01-24 5.2.10 transceiver enable/disable the layer-1 part of the siuc-x can be enabled/disabled by configuration (see figure 63 ) with the two bits tr_conf0.dis_tr and tr_conf2.dis_tx . by default all layer-1 functions with the exception of the transmitter buffer is enabled (dis_tr = ? 0 ? , dis_tx = ? 1 ? ). with several terminals connected to the s/t interface, another terminal may keep the interface activated although the siuc-x does not establish a connection. the receiver will monitor for incoming calls in this configuration. if the transceiver is disabled (dis_tr = ? 1 ? ) all layer-1 functions are disabled including the level detection circuit of the receiver. in this case the power consumption of the layer-1 is reduced to a minimum. the hdlc controller and codec part can still operate via iom-2. the dcl and fsc pins become input. figure 63 disabling of s/t transmitter 5.2.11 test functions the siuc-x provides test and diagnostic functions for the s/t interface: ? the internal local loop (internal loop a) is activated by a c/i command arl or by setting the bit lp_a (loop analog) in the tr_cmd register if the layer-1 statemachine is disabled. the transmit data of the transmitter is looped back internally to the receiver. the data of the iom-2 input b- and d-channels are looped back to the output b- and d- channels. the s/t interface level detector is enabled, i.e. if a level is detected this will be reported by the resynchronization indication (rsy) but the loop function is not affected. depending on the dis_tx bit in the tr_conf2 register the internal local loop can be transparent or non transparent to the s/t line. tr_conf2.dis_tx ? 1 ? ? 0 ? tr_conf0.dis_tr psb 2154 isdn module data sheet 144 2001-01-24 ? the external local loop (external loop a) is activated in the same way as the internal local loop described above. additionally the exlp bit in the tr_conf0 register has to be programmed and the loop has to be closed externally as described in figure 64 . the s/t interface level detector is disabled. this allows complete system diagnostics. ? in remote line loop (rlp) received data is looped back to the s/t interface. the d- channel information received from the line card is transparently forwarded to the output iom-2 d-channel. the output b-channel information on iom-2 is fixed to ? ff ? h while this test loop is active. the remote loop is programmable in tr_conf2.rlp. figure 64 external loop at the s/t-interface ? transmission of special test signals on the s/t interface according to the modified ami code are initiated via a c/i command written in cix0 register (see chapter 5.3.2 ) two kinds of test signals may be transmitted by the siuc-x: ? the single pulses are of alternating polarity. one pulse is transmitted in each frame resulting in a frequency of the fundamental mode of 2 khz. the corresponding c/i command is ssp (send single pulses). ? the continuous pulses are of alternating polarity. 48 pulses are transmitted in each frame resulting in a frequency of the fundamental mode of 96 khz. the corresponding c/i command is scp (send continuous pulses). scout-s(x) sx1 sx2 sr1 sr2 100 ? 100 ? psb 2154 isdn module data sheet 145 2001-01-24 5.3 control of layer-1 the layer-1 activation/ deactivation can be controlled by an internal state machine via the iom-2 c/i0 channel or by software via the microcontroller interface directly. in the default state the internal layer-1 state machine of the siuc-x is used. by setting the l1sw bit in the tr_conf0 register the internal state machine can be disabled and the layer-1 commands, which are normally generated by the internal state machine are written directly in the tr_cmd register or indications read from the tr_sta register respectively. the siuc-x layer-1 control flow is shown in figure 65 . it should be noted that the tr_cmd and tr_sta registers can always be read even if the layer-1 statemachine is enabled. this may be usefull for test purposes. figure 65 layer-1 control in the following sections the layer-1 control by the siuc-x state machine will be described. for the description of the iom-2 c/i0 channel see also chapter 5.5.5 . the layer-1 functions are controlled by commands issued via the cix0 register. these commands, sent over the iom-2 c/i channel 0 to layer 1, trigger certain procedures, such as activation/deactivation, switching of test loops and transmission of special pulse patterns. these procedures are governed by layer-1 state diagrams. responses from layer 1 are obtained by reading the cir0 register after a cic interrupt (ista). the state diagrams of the siuc-x are shown in figure 67 and figure 68 . the activation/deactivation implemented by the siuc-x agrees with the requirements set forth in itu recommendations. state identifiers f1-f8 are in accordance with itu i.430. psb 2154 isdn module data sheet 146 2001-01-24 state machines are the key to understanding the transceiver part of the siuc-x. they include all information relevant to the user and enable him to understand and predict the behaviour of the siuc-x. the state diagram notation is given in figure 66 . the informations contained in the state diagrams are: ? state name (based on itu i.430) ? s/t signal received (info) ? s/t signal transmitted (info) ? c/i code received ? c/i code transmitted ? transition criteria the coding of the c/i commands and indications are described in detail in chapter 5.3.2 . figure 66 state diagram notation the following example illustrates the use of a state diagram with an extract of the te state diagram. the state explained is ? f3 deactivated ? . the state may be entered: ? from the unconditional states (arl, res, tm) ? from state ? f3 pending deactivation ? , ? f3 power up ? , ? f4 pending activation ? or ? f5 unsynchronized ? after the c/i command ? di ? has been received. the following informations are transmitted: ? info 0 (no signal) is sent on the s/t-interface. ? c/i message ? dc ? is issued on the iom-2 interface. the state may be left by either of the following methods: ? leave for the state ? f3 power up ? in case c/i = ? tim ? code is received. ? leave for state ? f4 pending activation ? in case c/i = ar8 or ar10 is received. ? leave for the state ? f6 synchronized ? after info 2 has been recognized on the s/t- interface. ? leave for the state ? f7 activated ? after info 4 has been recognized on the s/t- interface. itd09657 cmd. ind. state c / unconditional transition s / t interface info out ipac in i x i r ipac iom-2 interface siuc-x psb 2154 isdn module data sheet 147 2001-01-24 ? leave for any unconditional state if any unconditional c/i command is received. as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a ? ? ? stands for a logical and combination. and a ? + ? indicates a logical or combination. the sections following the state diagram contain detailed information on all states and signals used. test signals send single pulses (ssp) one pulse with a width of one bit period per frame with alternating polarity. send continuous pulses (scp) continuous pulses with a pulse width of one bit period. external layer-1 statemachine instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. the internal layer-1 statemachine can be disabled by setting the l1sw bit in the tr_conf0 register to ? 1 ? . the transmitter is completely under control of the microcontroller via register tr_cmd. the status of the receiver is stored in register tr_sta and has to be evaluated by the microcontroller. this register is updated continuously. if not masked a ric interrupt is generated by any change of the register contents. the interrupt is cleared after a read access to this register. the ric interrupt can also be used if the inchip layer-1 statemachine is enabled. this is not required in most applications as the important status changes will result in c/i code change interrupts. however, ric provides the advantage that status changes on s can be indicated much faster to the c then a c/i code change interrupt. reset states an active signal on the reset pin reset brings the transceiver state machine to the reset state. the function of this reset event is identical to the c/i code res concerning the state machine. c/i codes in reset state in the reset state the c/i code 0001 (res) is valid. this state is entered either after a hardware reset (reset ) or after the c/i code res. psb 2154 isdn module data sheet 148 2001-01-24 5.3.1 state machine te mode 5.3.1.1 state transition diagram (te) figure 67 shows the state transition diagram of the siuc-x state machine. figure 68 shows this for the unconditional transitions (reset, loop, test mode i). figure 67 state transition diagram (te) x 1) drfortransitionfromf7orf8 dr6fortransitionfromf6 2) ar stands for ar8 or ar10 3) ai stands for ai8 or ai10 4) x stands for commands initiating unconditional transitions (res, arl, ssp or scp) to1: 16 ms to2: 0.5 ms statem_te_s.vsd f3 pending deact. dr 1) i0 i0 f3 deactivated dc di i0 i0 ar i2 tim i0*to1 f3 power up pu tim i0 i0 di tim di i2 di*to2 tim*to2 i0 f8 lost framing rsy i0 x i4 i0*to1 i0*to1 ar di i2 f7 activated ai 3) ar 2) i3 i4 f6 synchronized ar i3 i2 x f5 unsynchronized rsy i0 ix i2 i0 f4 pending act. pu ar 2) i1 i0 x i4 i2 i2 i4 ix ix tim i4 i4 i4 tim di tim x 4) uncond. state x di psb 2154 isdn module data sheet 149 2001-01-24 figure 68 state transition diagram of unconditional transitions (te) 5.3.1.2 states (te) f3 pending deactivation state after deactivation from the s/t interface by info 0. note that no activation from the terminal side is possible starting from this state. a ? di ? command has to be issued to enter the state ? deactivated state ? . f3 deactivated state the s/t interface is deactivated and the clocks are deactivated 500 s after entering this state and receiving info 0 if the cfs bit of the siuc-x configuration register is set to ? 0 ? . activation is possible from the s/t interface and from the iom-2 interface. the bit tr_cmd.pd is set and the analog part is powered down (tr_cmd.pd is only set if istatr.ld is inactive). f3 power up the s/t interface is deactivated (info 0 on the line) and the clocks are running. f4 pending activation the siuc-x transmits info 1 towards the network, waiting for info 2. statem_te_aloop_s.vsd loop a activated ail rsy arl i3 * loop a closed arl arl i3 * di tim di tim arl reset res res i0 * di tim test mode i tma ssp scp it i * di tim i3 i3 res any state rst ssp + scp any state except test mode i psb 2154 isdn module data sheet 150 2001-01-24 f5 unsynchronized any signal except info 2 or 4 detected on the s/t interface. f6 synchronized the receiver has synchronized and detects info 2. info 3 is transmitted to synchronize the nt. f7 activated the receiver has synchronized and detects info 4. all user channels are now conveyed transparently to the iom-2 interface. to transfer user channels transparently to the s/t interface either the command ar8 or ar10 has to be issued and tr_sta.fsyn must be ? 1 ? (signal from remote side must be synchronous). f8 lost framing the receiver has lost synchronization in the states f6 or f7 respectively. unconditional states loop a closed (internal or external) the siuc-x loops back the transmitter to the receiver and activates by transmission of info 3. the receiver has not yet synchronized. for a non transparent internal loop the dis_tx bit of register tr_conf2 has to be set to ? 1 ? . loop a activated (internal or external) the receiver has synchronized to info 3. data may be sent. the indication ? ail ? is output to indicate the activated state. if the loop is closed internally and the s/t line awake detector detects any signal on the s/t interface, this is indicated by ? rsy ? . test mode - ssp single alternating pulses are transmitted to the s/t-interface resulting in a frequency of the fundamental mode of 2 khz. test mode - scp continuous alternating pulses are transmitted to the s/t-interface resulting in a frequency of the fundamental mode of 96 khz. psb 2154 isdn module data sheet 151 2001-01-24 5.3.1.3 c/i codes (te) note: in the activated states (ai8, ai10 or ail indication) the 2b+d channels are only transferred transparently to the s/t interface if one of the three ? activation request ? commands is permanently issued. command abbr. code remark activation request with priority class 8 ar8 1000 activation requested by the siuc-x, d- channel priority set to 8 ( see note ) activation request with priority class 10 ar10 1001 activation requested by the siuc-x, d- channel priority set to 10 ( see note ) activation request loop arl 1010 activation requested for the internal or external loop a ( see note ). for a non transparent internal loop bit dis_tx of register tr_conf2 has to be set to ? 1 ? additionally. deactivation indication di 1111 deactivation indication reset res 0001 reset of the layer-1 statemachine timing tim 0000 layer-2 device requires clocks to be activated test mode ssp ssp 0010 one ami-coded pulse transmitted in each frame, resulting in a frequency of the fundamental mode of 2 khz test mode scp scp 0011 ami-coded pulses transmitted continuously, resulting in a frequency of the fundamental mode of 96 khz indication abbr. code remark deactivation request dr 0000 deactivation request via s/t-interface if left from f7/f8 reset res 0001 reset acknowledge test mode acknowledge tma 0010 acknowledge for both ssp and scp resynchronization during level detect rsy 0100 signal received, receiver not synchronous deactivation request from f6 dr6 0101 deactivation request from state f6 psb 2154 isdn module data sheet 152 2001-01-24 power up pu 0111 iom-2 interface clocking is provided activation request ar 1000 info 2 received activation request loop arl 1010 internal or external loop a closed illegal code violation cvr 1011 illegal code violation received. this function has to be enabled by setting the en_icv bit of register tr_conf0. activation indication loop ail 1110 internal or external loop a activated activation indication with priority class 8 ai8 1100 info 4 received, d-channel priority is 8 or 9. activation indication with priority class 10 ai10 1101 info 4 received, d-channel priority is 10 or 11. deactivation confirmation dc 1111 clocks are disabled if cfs bit of register mode1 is set to ? 1 ? , quiescent state indication abbr. code remark psb 2154 isdn module data sheet 153 2001-01-24 5.3.1.4 infos on s/t (te) receive infos on s/t (downstream) transmit infos on s/t (upstream) name abbr. description info 0 i0 no signal on s/t info 2 i2 4 khz frame a= ? 0 ? info 4 i4 4 khz frame a= ? 1 ? info x ix any signal except info 2 or info 4 name abbr. description info 0 i0 no signal on s/t info 1 i1 continuous bit sequence of the form ? 00111111 ? info 3 i3 4 khz frame test info 1 it 1 ssp - send single pulses test info 2 it 2 scp - send continuous pulses psb 2154 isdn module data sheet 154 2001-01-24 5.3.2 command/ indicate channel codes (c/i0) - overview the table below presents all defined c/i0 codes. a command needs to be applied continuously until the desired action has been initiated. indications are strictly state orientated. refer to the state diagrams in the previous sections for commands and indications applicable in various states. code te cmd ind 0000tim dr 0001res res 0010ssp tma 0011scp ? 0100 ? rsy 0101 ? dr6 0110 ?? 0111 ? pu 1000ar8 ar 1001ar10 ? 1010arl arl 1011 ? cvr 1100 ? ai8 1101 ? ai10 1110 ? ail 1111di dc psb 2154 isdn module data sheet 155 2001-01-24 5.4 control procedures 5.4.1 example of activation/deactivation an example of an activation/deactivation of the s/t interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in figure 69 . figure 69 example of activation/deactivation initiated by the terminal a_deact.dr w psb 2154 isdn module data sheet 156 2001-01-24 5.4.2 activation initiated by the terminal info 1 has to be transmitted as long as info 0 is received. info 0 has to be transmitted thereafter as long as no valid info (info 2 or info 4) is received. after reception of info 2 or info 4 transmission of info 3 has to be started. data can be transmitted if info 4 has been received. figure 70 example of activation/deactivation initiated by the terminal (te). activation/deactivation completely under software control note: rinf and xinf are receive- and transmit-infos of register tr_sta. act_deac_te-ext_s.vsd xinf='000' rinf='01' rinf='10' xinf='011' info 1 info 0 info 2 info 0 info 3 info 4 xinf='010' t1 te info 0 info 0 info 0 xinf='000' te nt s/t interface c interface t1 te : 2to6 frames(0.5msto1.5ms) t3 te : 4 frames (1 ms) t2 te : 2 frames (0.5 ms) t3 te rinf='00' t2 te rinf='11' tddis='1', tddis='0' tddis='1', psb 2154 isdn module data sheet 157 2001-01-24 5.4.3 activation initiated by the network termination nt info 0 has to be transmitted as long as no valid info (info 2 or info 4) is received. after reception of info 2 or info 4 transmission of info 3 has to be started. data can be transmitted if info 4 has been received. figure 71 example of activation/deactivation initiated by the network termination (nt). activation/deactivation completely under software control note: rinf and xinf are receive- and transmit-infos of register tr_sta. act_deac_lt_ext_s.vsd rinf='01' rinf='10' xinf='011' info 0 info 2 info 3 info 4 rinf='11' t1 te info 0 info 0 info 0 t2 te t3 te xinf='000' rinf='00' te nt s/t interface c interface t1 te : 2 to 6 s/t frames (0.5 ms to 1.5 ms) t3 te :4s/tframes(1ms) t2 te :2s/tframes(0.5ms) tddis='1', tddis='0' tddis='1', psb 2154 isdn module data sheet 158 2001-01-24 5.5 iom-2 interface the siuc-x supports the iom-2 interface in linecard mode and in terminal mode with single clock and double clock. the iom-2 interface consists of four lines: fsc, dcl, dd and du. the rising edge of fsc indicates the start of an iom-2 frame. the dcl and the bcl clock signals synchronize the data transfer on both data lines du and dd. the dcl is twice the bit rate, the bcl rate is equal to the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle and sampled at the falling edge of the second clock cycle. the iom-2 interface can be enabled/disabled with the dis_iom bit in the iom_cr register. a dcl signal and bcl signal (pin bcl/sclk) output is provided and the fsc signal is generated by the receive dpll which synchronizes it to the received s/t frame. the bcl clock together with the serial data strobe signal sds/rsto (multiplexed with reset output) can be used to connect time slot oriented standard devices to the iom-2 interface. if the transceiver is disabled (tr_conf0.dis_tr) the dcl and fsc pins become input and the hdlc part can still work via iom-2. in this case the clock mode bit (iom_cr.clkm) selects between a double clock and a single clock input for dcl. the clock rate/frequency of the iom-2 signals in te mode are: dd, du: 768 kbit/s fsc (o): 8 khz dcl (o): 1536 khz (double clock rate) bcl (o): 768 khz (single clock rate) option - transceiver disabled (dis_tr = ? 1 ? ): fsc (i): 8 khz dcl (i): 1536 ... 4096 khz, in steps of 512 khz (double clock rate) psb 2154 isdn module data sheet 159 2001-01-24 iom-2 frame structure (te mode) the frame structure on the iom-2 data ports (du,dd) of a master device in iom-2 terminal mode is shown in figure 72 . figure 72 iom-2 frame structure in terminal mode the frame is composed of three channels channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (mon0) and a command/indication channel (ci0) for control and programming of the layer-1 transceiver. channel 1 contains two 64-kbit/s intercommunication channels (ic) plus a monitor and command/indicate channel (mon1, ci1) to program or transfer data to other iom- 2 devices. channel 2 is used for the d-channel access mechanism (tlc-bus, s/g-bit). additionally, channel 2 supports further ic and mon channels. psb 2154 isdn module data sheet 160 2001-01-24 5.5.1 iom-2 handler the iom-2 handler offers a great flexibility for handling the data transfer between the different functional units of the siuc-x and voice/data devices connected to the iom-2 interface. additionally it provides a microcontroller access to all timeslots of the iom-2 interface via the four controller data access registers (cda). figure 73 shows the architecture of the iom-2 handler. for illustrating the functional description it contains all configuration and control registers of the iom-2 handler. the pcm data of the functional units transceiver (tr) and the controller data access (cda) b-channel hdlc controllers can be configured by programming the time slot and data port selection registers (tsdp). with the tss bits (time slot selection) the pcm data of the functional units can be assigned to each of the 32 pcm time slots of the iom-2 frame. with the dps bit (data port selection) the output of each functional unit is assigned to du or dd respectively. the input is assigned vice versa. with the data control registers (xxx_cr) the access to the data of the functional units can be controlled by setting the corresponding control bits (en, swap). the iom-2 handler also provides access to the monitor channel (mon) c/i channels (c/i0,c/i1) tic bus (tic) and hdlc control the access to these channels is controlled by the registers tr_cr, mon_cr, dci_cr and bchx_cr. the iom-2 interface with the serial data strobe sds is controlled by the control registers iom_cr and sds_cr. the reset configuration of the siuc-x iom-2 handler corresponds to the defined frame structure and data ports of a master device in iom-2 terminal mode (see figure 72 ). psb 2154 isdn module data sheet 161 2001-01-24 . figure 73 architecture of the iom handler (example configuration) 21150_07 cda control ( dps, tss, en_tbm, swap, en_i1/0, en_o1/0, mcdaxy, stixy, stovxy, ackxy ) cda registers cda10 cda11 cda20 cda21 cda_tsdpxy cdax_crx mcda sti msti asti controller data access (cda) control monitor data (dps, cs2-0, en_mon) mon_cr tic bus disable (tic_dis) iom_cr dci_cr c/i1 (dps_ci1, en_ci1) control transceiver data access (dps, tss, cs2-0, en_d, en_b1r, en_b1x, en_b2r, en_b2x ) tr_tsdp_bc1 tr_tsdp_bc2 trc_cr ddata d, b1, b2, c/i0 data c/i1 data c/i0 data tic bus data monitor data cda data b1 data b2 data transceiver data tr d-channel rx/tx b1-channel rx b1-channel tx mon handler tic c/i0 c/i1 data d-ch b1-ch b2-ch fifos microcontroller interface sds1/2_cr iom_cr ( ens_tss, ens_tss+1, ens_tss+3, tss, sdsx_bcl iom-2 interface du dd fsc dcl bcl/sclk sds1 sds2 iom-2 handler c/i0 (cs2-0) dcic_cr control hdlc channel data d (cs2-0, d_en_d, d_en_b1, d_en_b2) b1 (dps, tss, dps_d, en_d, en_bc1, en_bc2, cs2-0) bcha_tsdp _b1/2, bcha_cr bchb_tsdp _b1/2, bchb_cr b2 (dps, tss, dps_d, en_d, en_bc1, en_bc2, cs2-0) control c/i data b2-channel rx b2-channel tx sds1/2_cr en_bcl, clkm, dis_od, dis_iom, diom_inv, diom_sds note: the registers shown above are used to control the corresponding functional block (e.g. programming of timeslot, data port, enabling/disabling, etc.) psb 2154 isdn module data sheet 162 2001-01-24 5.5.1.1 controller data access (cda) with its four controller data access registers (cda10, cda11, cda20, cda21) the siuc-x iom-2 handler provides a very flexible solution for the host access to up to 32 iom-2 time slots. the functional unit cda (controller data access) allows with its control and configuration registers looping of up to four independent pcm channels from du to dd or vice versa over the four cda registers shifting of two independent pcm channels to another two independent pcm channels on both data ports (du, dd). between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. if this is not the case a switching function is performed monitoring of up to four time slots on the iom-2 interface simultaneously microcontroller read and write access to each pcm timeslot the access principle which is identical for the two channel register pairs cda10/11 and cda20/21 is illustrated in figure 74 . each of the index variables x,y used in the following description can be 1 or 2 for x and 0 or 1 for y. the prefix ? cda_ ? from the register names has been omitted for simplification. to each of the four cdaxy data registers a tsdpxy register is assigned by which the time slot and the data port can be determined. with the tss (time slot selection) bits a time slot from 0...31 can be selected. with the dps (data port selection) bit the output of the cdaxy register can be assigned to du or dd respectively. the time slot and data port for the output of cdaxy is always defined by its own tsdpxy register. the input of cdaxy depends on the swap bit in the control registers crx. if the swap bit = ? 0 ? (swap is disabled) the time slot and data port for the input and output of the cdaxy register is defined by its own tsdpxy register. if the swap bit = ? 1 ? (swap is enabled) the input port and timeslot of the cdax0 is defined by the tsdp register of cdax1 and the input port and timeslot of cdax1 is defined by the tsdp register of cdax0. the input definition for timeslot and data port cdax0 are thus swapped to cdax1 and for cdax1 swapped to cdax0. the output timeslots are not affected by swap. the input and output of every cdaxy register can be enabled or disabled by setting the corresponding en (-able) bit in the control register cdax_cr. if the input of a register is disabled the output value in the register is retained. in the normal mode (swap=0) the input of cdax0 and cdax1 is enabled via en_i0 and en_i1, respectively. if swap=1 en_i0 controls the input of cdax1 and en_i1 controls the input of cdax0. the output control (en_o0 and en_o1) is not affected by swap. usually one input and one output of a functional unit (transceiver, hdlc controllers, cda registers) is programmed to a timeslot of iom-2 (e.g. for b-channel transmission in upstream direction the hdlc controller writes data onto iom and the transceiver reads psb 2154 isdn module data sheet 163 2001-01-24 data from iom). for monitoring data in such cases a cda register is programmed as described below under ? monitoring data ? . besides that none of the iom timeslots must be assigned more than one input and output of any functional unit. . figure 74 data access via cdax1 and cdax2 register pairs looping and shifting data figure 75 gives examples for typical configurations with the above explained control and configuration possibilities with the bits tss, dps, en and swap in the registers tsdpxy or cdax_cr: a) looping iom-2 time slot data from du to dd or vice versa (swap = 0) b) shifting data from tsa to tsb and tsc to tsd in both transmission directions (swap = 1) c) switching data from tsa to tsb and looping from du to dd or tsc to tsd and looping from dd to du respectively tsa is programmed in tsdp10, tsb in tsdp11, tsc in tsdp20 and tsd in tsdp21. it should also be noted that the input control of cda registers is swapped if swap=1 while the output control is not affected (e.g. for cda11 in example a: en_i1=1 and en_o1=1, whereas for cda11 in example b: en_i0=1 and en_o1=1). du cdax1 control register cda_crx dd 1 1 time slot selection (tss) 1 x = 1 or 2; a,b = 0...63 data port cda_tsdpx1 0 1 0 1 1 0 1 1 enable input (en_o0) output cda_tsdpx0 1 0 cdax0 1 (en_i0) (en_i1) input enable output (en_o1) selection (dps) data port selection (dps) selection (tss) time slot tsa tsa tsb tsb input swap (swap) note: the maximum number of timeslots is 64, however this value can be different if required by a specific project. psb 2154 isdn module data sheet 164 2001-01-24 figure 75 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) shifting and looping data tsa tsb tsc tsd cda10 cda11 cda20 cda21 tsa tsb tsc tsd du dd tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd b) shifting d ata a) looping data .tss: .dps .swap ? 0 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? tsa tsb tsc tsd .tss: .dps .swap ? 1 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd c) s witching d ata tsa tsb tsc tsd .tss: .dps .swap ? 1 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 1 ? psb 2154 isdn module data sheet 165 2001-01-24 figure 76 shows the timing of looping tsa from du to dd (a = 0...11) via cdaxy register. tsa is read in the cdaxy register from du and is written one frame later on dd. . figure 76 data access when looping tsa from du to dd figure 77 shows the timing of shifting data from tsa to tsb on du(dd). in figure 77a) shifting is done in one frame because tsa and tsb didn ? t succeed direct one another (a,b = 0...9 and b a+2) . in figure 77b) shifting is done from one frame to the following frame. this is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). at looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). sti and stov are explained in the section ? synchronous transfer ? . if there is no controller intervention the looping and shifting is done autonomous. tsa du tsa fsc cdaxy c rd wr ack stov tsa dd tsa sti a = 0...11 *) if access by the c is required *) psb 2154 isdn module data sheet 166 2001-01-24 figure 77 data access when shifting tsa to tsb on du (dd) tsa du tsb fsc cdaxy c rd wr ack stov sti tsa sti tsa fsc cdaxy c rd wr ack stov sti tsb tsa tsb (dd) (a,b: 0...11 and (b = a+1 or b psb 2154 isdn module data sheet 168 2001-01-24 synchronous transfer while looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). the microcontroller access to the cdaxy registers can be synchronized by means of four programmable synchronous transfer interrupts (stixy) and synchronous transfer overflow interrupts (stovxy) in the sti register. depending on the dps bit in the corresponding cda_tsdpxy register the stixy is generated two (for dps= ? 0 ? ) or one (for dps= ? 1 ? ) bcl clock after the selected time slot (cda_tsdpxy.tss). one bcl clock is equivalent to two dcl clocks. it should be noted that synchronous interrupts are only generated if the corresponding cda register input is enabled even if the synchronous interrupts are used for any other purpose than cda register access. in order to enable the sti interrupts the input of the corresponding cda register has to be enabled. this is also valid if only a synchronous write access (output) is wanted. the enabling of the output alone does not effect an sti interrrupt. in order to enable the stov interrupts the output of the corresponding cda register has to be enabled. in the following description the index xy 0 and xy 1 are used to refer to two different interrupt pairs (sti/stov) out of the four cda interrupt pairs (sti10/stov10, sti11/ stov11, sti20/stov20, sti21/stov21). an stovxy 0 is related to its stixy 0 and is only generated if stixy 0 is enabled and not acknowledged. however, if stixy 0 is masked, the stovxy 0 is generated for any other stixy 1 which is enabled and not acknowledged. table 22 gives some examples for that. it is assumed that an stov interrupt is only generated because an sti interrupt was not acknowledged before. in example 1 only the stixy 0 is enabled and thus stixy 0 is only generated. if no sti is enabled, no interrupt will be generated even if stov is enabled (example 2). in example 3 stixy 0 is enabled and generated and the corresponding stovxy 0 is disabled. stixy 1 is disabled but its stovxy 1 is enabled, and therefore stovxy 1 is generated due to stixy 0 . in example 4 additionally the corresponding stovxy 0 is enabled, so stovxy 0 and stovxy 1 are both generated due to stixy 0 . in example 5 additionally the stixy 1 is enabled with the result that stovxy 0 is only generated due to stixy 0 and stovxy 1 is only generated due to stixy 1 . compared to the previous example stovxy 0 is disabled in example 6, so stovxy 0 is not generated and stovxy 1 is only generated for stixy 1 but not for stixy 0 . compared to example 5 in example 7 a third stovxy 2 is enabled and thus stovxy2 is generated additionally for both stixy 0 and stixy 1 . psb 2154 isdn module data sheet 169 2001-01-24 an stov interrupt is not generated if all stimulating sti interrupts are acknowledged. an stixy must be acknowledged by setting the ackxy bit in the asti register until two bcl clocks (for dps= ? 0 ? ) or one bcl clocks (for dps= ? 1 ? ) before the time slot which is selected for the appropriate stixy. the interrupt structure of the synchronous transfer is shown in figure 79 . . figure 79 interrupt structure of the synchronous data transfer figure 80 shows some examples based on the timeslot structure. figure a) shows at which point in time an sti and stov interrrupt is generated for a specific timeslot. figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. table 22 examples for synchronous transfer interrupts enabled interrupts (register msti) generated interrupts (register sti) sti stov sti stov xy 0 -xy 0 - example 1 -xy 0 - - example 2 xy 0 xy 1 xy 0 xy 1 example 3 xy 0 xy 0 ; xy 1 xy 0 xy 0 ; xy 1 example 4 xy 0 ; xy 1 xy 0 ; xy 1 xy 0 xy 1 xy 0 xy 1 example 5 xy 0 ; xy 1 xy 1 xy 0 xy 1 - xy 1 example 6 xy 0 ; xy 1 xy 0 ; xy 1 ; xy 2 xy 0 xy 1 xy 0 ; xy 2 xy 1 ; xy 2 example 7 sti11 msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 ack11 asti ack10 ack20 ack21 st icb mos tran icd cic aux interrupt ista ien1 st ica psb 2154 isdn module data sheet 170 2001-01-24 . figure 80 examples for the synchronous transfer interrupt control with one enabled stixy xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 a) interrupts for data access to time slot 0 (b1 after reset), msti.sti10 and msti.stov10 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '1' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 b) interrupts for data access to time slot 0 (b1 after reset), stov interrupt used as flag for "intermediate cda access"; msti.sti10 and msti.stov21 enabled c) interrupts for data access to time slot 0 and 5, msti.sti10, msti.stov10, msti.sti21 and msti.stov21 enabled sti_stov.vsd xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '0' '1' msti.stovxy: '0' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 d) interrupts for data access to time slot 0 (b1 after reset), stov21 interrupt used as flag for "intermiediate cda access", stov10 interrupt used as flag for "cda access failed"; msti.sti10, msti.stov10 and msti.stov21 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '0' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 : stov interrupt generated for a not acknowledged sti interrupt : sti interrupt generated psb 2154 isdn module data sheet 171 2001-01-24 5.5.2 idsl support 5.5.2.1 iom-2 interface the iom handler of the siuc-x provides a flexible access of the b-channel hdlc controllers to the timeslots on iom-2 which may be used for idsl applications. one of the two b-channel hdcl controllers is programmed to transparent mode and its fifo is programmed to a certain timeslot on iom-2, while the second b-channel controller and the d-channel controller is unused ( figure 81 ) . figure 81 timeslot assignment on iom-2 this b-channel hdlc controller is assigned to three timeslots on iom-2, which are two 8-bit timeslots and one 2-bit timeslot. for each of the 3 timeslots the timeslot position (timeslot number) and data port (du, dd) can individually be selected. additionally, each of the 3 timeslots can individually be enabled/disabled so any combination of the 3 timeslots can be configured, i.e. during each fsc frame the hdlc/fifo will access 2 bit, 8 bit, 10 bit, 16 bit or 18 bit. some examples for access to iom timeslots are given in figure 82 : example 1 shows 18-bit access to b1 + b2 + d example 2 shows 10-bit access to b2 + d example 3 shows 10-bit access to b1 + d in channel 1 example 4 shows 16-bit access to mon0 + mon1. b-channel hdlc 1 tx/rx fifos b-channel hdlc 2 tx/rx fifos d-channel hdlc tx/rx fifos s transceiver iom-2 interface host s timeslot assignement of fifo data to iom-2 timeslots (described in this chapter) psb 2154 isdn module data sheet 172 2001-01-24 . figure 82 examples for hdlc controller access the following registers are used to configure one of the two b-channel hdlc controllers (channel a or b) for that (x = a or b): bchx_tsdp_bc1 consists of bits for timeslot selection (tss) and data port selection (dps) to program the first 8-bit timeslot. bchx_tsdp_bc2 consists of bits for timeslot selection (tss) and data port selection (dps) to program the second 8-bit timeslot. bchx_cr consists of bits for channel selection (cs2-0) and data port selection (dps_d) to program the 2-bit timeslot. another 3 bits are used to selectively enable/ disable the first 8-bit timeslot (en_bc1), the second 8-bit timeslot (en_bc2) and the 2-bit timeslot (en_d). 21550_24 b1 b2 d channel 0 channel 1 channel 2 fsc du/dd hdlc controller access: example 1 example 2 example 3 example 4 psb 2154 isdn module data sheet 173 2001-01-24 5.5.2.2 s interface data which is read from and written to the iom-2 interface by the b-channel controller as described in the previous chapter 5.5.2.1 is received from and transmitted to the s interface ( figure 83 ). . figure 83 timeslot assignment on s as the timeslot structure of the iom-2 interface is different from the s interface, it is important to consider the delay and mapping of data between both interfaces figure 83 shows the example for bundling 2b+d channels for transmission of 144 kbit/s. serial data from the fifo is mapped to the corresponding b- and d-channel timeslots on iom-2. the itu i.430 specifies the order and timeslot position of b- and d-channel data on the s-frame. due to that the order of b- and d-channel data on s is different from iom-2 which has the effect that mapping of data from iom-2 to s will change the original order of the serial data stream. however, this has no effect as the remote receiver is using the same mechanism for mapping data between s and iom-2. in siuc-x b- and d-channel bits of one iom-frame are mapped to the corresponding timeslots of the same s-frame. . figure 84 mapping of bits from iom-2 to s b-channel hdlc 1 tx/rx fifos b-channel hdlc 2 tx/rx fifos d-channel hdlc tx/rx fifos s transceiver iom-2 interface host s mapping of data between iom-2 and s-interface (described in this chapter) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 next fsc-frame mapping of serial data on iom-2 1 2 3 4 5 6 7 8 b1 b2 9 10 11 12 13 14 15 16 d 17 18 19 20 serial data in fifo 17 18 mapping from iom-2tos 1 2 3 4 5 6 7 8 b1 b2 9 10 11 12 13 14 15 16 d d psb 2154 isdn module data sheet 174 2001-01-24 5.5.3 serial data strobe signal and strobed data clock for time slot oriented standard devices connected to the iom-2 interface the siuc-x provides an independent data strobe signal sds which is multiplexed with the reset output signal (sds/rsto ). instead of a data strobe signal a strobed iom-2 bit clock can be provided on pin sds. 5.5.3.1 serial data strobe signal the strobe signal can be generated with every 8-khz frame and is controlled by the registers sds_cr. by programming the tss bits and three enable bits (ens_tss, ens_tss+1, ens_tss+3) a data strobe can be generated for the iom-2 time slots ts, ts+1 and ts+3 and any combination of them. the data strobes for ts and ts+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for ts+3 is always 2 bits long (bit7, bit6). figure 85 shows three examples for the generation of a strobe signal. in example 1 the sds is active during channel b2 on iom-2 whereas in the second example during ic2 and mon1. the third example shows a strobe signal for 2b+d channels which can be used e.g. for an idsl (144kbit/s) transmission. the timeslot programming for the sds signals can be used for another purpose besides sds signal generation. if enabled (sds_conf.diom_sds=1) the du/dd lines on iom are high impedant in the selected timeslots (sds_conf.diom_inv=1) or vice versa (diom_inv=0), meaning that only the selected timeslot is active and du/dd are high impedant outside this timeslot. in this way the iom-2 interface can be used as real standard pcm interface where data can be transferred in any timeslot. psb 2154 isdn module data sheet 175 2001-01-24 figure 85 data strobe signal fsc dd,du m r m x d ci0 sds (example1) sds (example2) sds (example3) tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' ='0' ='1' ='0' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' ='1' ='1' ='0' tss ens_tss ens_tss+1 ens_tss+3 example 3: = '0 h ' ='1' ='1' ='1' ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 2154_17 for all examples sds_conf.sds_bcl must be set to ? 0 ? . psb 2154 isdn module data sheet 176 2001-01-24 5.5.3.2 strobed iom-2 bit clock the strobed iom-2 bit clock is active during the programmed window. outside the programmed window a ? 0 ? is driven. two examples are shown in figure 86 . figure 86 strobed iom-2 bit clock. register sds_conf programmed to 01 h the strobed bit clock can be enabled in sds_conf.sds_bcl. for all examples sds_conf.sds_bcl must be set to ? 1 ? . fsc dd,du m r m x d ci0 sds (example1) sds (example2) ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 2154_18 tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' ='0' ='0' ='1' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' ='1' ='1' ='0' setting of sds_cr: psb 2154 isdn module data sheet 177 2001-01-24 5.5.4 iom-2 monitor channel the iom-2 monitor channel (see figure 87 ) is utilized for information exchange in the monitor channel between a master mode device and a slave mode device. the montior channel data can be controlled by the bits in the monitor control register (mon_cr). for the transmission of the monitor data one of the iom-2 channels (3 iom-2 channels in te mode) can be selected by setting the monitor channel selection bits (mcs) in the monitor control register (mon_cr). the dps bit in the same register selects between an output on du or dd respectively and with en_mon the monitor data can be enabled/disabled. the default value is monitor channel 0 (mon0) enabled and transmission on dd. figure 87 examples of monitor channel applications in iom-2 te mode the monitor channel of the siuc-x can be used in following applications which are illustrated in figure 87 : as a master device the siuc-x can program and control other devices attached to the iom-2 which do not need a parallel microcontroller interface e.g. arcofi-ba psb 2161. this facilitates redesigning existing terminal designs in which e.g. an interface of an expansion slot is realized with iom-2 interface and monitor programming. 2154_66.vsd monitor handler layer 1 v/d module (e.g. arcofi-ba) iom-2 monitor channel siuc c siuc as master device monitor handler layer 1 v/d module (e.g. isar34) iom-2 monitor channel siuc c data exchange between two c systems c psb 2154 isdn module data sheet 178 2001-01-24 for data exchange between two microcontroller systems attached to two different devices on one iom-2 backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path between the two systems. this simplifies the system design of terminal equipment. 5.5.4.1 handshake procedure the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted once per 8-khz frame until the transfer is acknowledged via the mr bit. the monitor channel protocol is described in the following section and figure 88 illustrates this. the relevant control and status bits for transmission and reception are listed in table 23 and table 24 . table 23 transmit direction control/ status bit register bit function control mocr mxc mx bit control mie transmit interrupt enable status mosr mda data acknowledged mab data abort msta mac transmission active table 24 receive direction control/ status bit register bit function control mocr mrc mr bit control mre receive interrupt enable status mosr mdr data received mer end of reception psb 2154 isdn module data sheet 179 2001-01-24 figure 88 monitor channel protocol (iom-2) itd10032 mon mx transmitter mr 1 1 ff ff 1 1 adr 0 1 0 0 data1 0 1 data1 adr 0 0 data1 0 1 data1 0 0 0 0 data2 0 1 data2 data2 0 1 data2 0 0 ff 1 0 ff 1 0 ff 1 1 ff 1 1 receiver mie = 1 mox = adr mxc = 1 mac = 1 mox = data1 mda int. mda int. mda int. mxc = 0 mdr int. rd mor (=adr) mrc = 1 mdr int. mdr int. mrc = 0 mer int. p p 125 s rd mor (=data1) rd mor (=data2) mox = data2 mac = 0 psb 2154 isdn module data sheet 180 2001-01-24 before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a ? 0 ? in the monitor channel active mac status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to ? 1 ? . this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive mor register and generates an mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to ? 1 ? to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor interrupt enable (mie) to ? 1 ? . as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to ? 0 ? . this causes a monitor data acknowledge mda interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate an mda interrupt status. this "mda interrupt ? write data ? mdr interrupt ? read data ? mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit mxc to ? 0 ? . this enforces an inactive ( ? 1 ? ) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception mer interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active mac bit return to ? 0 ? . during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to ? 0 ? . an aborted transmission is indicated by a monitor channel data abort mab interrupt status at the transmitter. the monitor transfer protocol rules are summarized in the following section: psb 2154 isdn module data sheet 181 2001-01-24 a pair of mx and mr in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission . a start of a transmission is initiated by the transmitter by setting the mxc bit to ? 1 ? enabling the internal mx control. the receiver acknowledges the received first byte by setting the mr control bit to ? 1 ? enabling the internal mr control. the internal mx,mr control indicates or acknowledges a new byte in the mon slot by toggling mx,mr from the active to the inactive state for one frame. two frames with the mr-bit set to inactive indicate a receiver request for abort . the transmitter can delay a transmission sequence by sending the same byte continuously. in that case the mx-bit remains active in the iom-2 frame following the first byte occurrence. delaying a transmission sequence is only possible while the receiver mr-bit and the transmitter mx-bit are active. since a double last-look criterion is implemented the receiver is able to receive the mon slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. to control this handshake procedure a collision detection mechanism is implemented in the transmitter. this is done by making a collision check per bit on the transmitted monitor data and the mx bit. monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. two frames with the mx bit in the inactive state indicates the end of a message (eom). transmission and reception of monitor messages can be performed simultaneously. this feature is used by the siuc-x to send back the response before the transmission from the controller is completed (the siuc-x does not wait for eom from controller). 5.5.4.2 error treatment in case the siuc-x does not detect identical monitor messages in two successive frames, transmission is not aborted. instead the siuc-x will wait until two identical bytes are received in succession. a transmission is aborted of the siuc-x if an error in the mr handshaking occurs a collision on the iom-2 bus of the monitor data or mx bit occurs the transmission time-out timer expires a reception is aborted by the device if an error in the mx handshaking occurs or an abort request from the opposite device occurs psb 2154 isdn module data sheet 182 2001-01-24 mx/mr treatment in error case in the master mode the mx/mr bits are under control of the microcontroller through mxc or mrc, respectively. an abort is indicated by an mab interrupt or mer interrupt, respectively. in the slave mode the mx/mr bits are under control of the device. an abort is always indicated by setting the mx/mr bit inactive for two or more iom-2 frames. the controller must react with eom. figure 89 shows an example for an abort requested by the receiver, figure 90 shows an example for an abort requested by the transmitter and figure 91 shows an example for a successful transmission. figure 89 monitor channel, transmission abort requested by the receiver figure 90 monitor channel, transmission abort requested by the transmitter mx (du) iom -2 frame no. 1 2 345 67 eom mr (dd) 1 0 1 0 mon_rec-abort.vsd abort request from receiver mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_tx-abort.vsd abort request from transmitter psb 2154 isdn module data sheet 183 2001-01-24 figure 91 monitor channel, normal end of transmission 5.5.4.3 monitor channel programming as a master device as a master device the siuc-x can program and control other devices attached to the iom-2 interface. the master mode is selected by default if one of the possible microcontroller interfaces are selected. the monitor data is written by the microprocessor in the mox register and transmitted via iom-2 dd (du) line to the programmed/controlled device e.g. arcofi-ba psb 2161 or iec-q te psb 21911. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter chapter 5.5.4.1 . if the transmitted command was a read command the slave device responds by sending the requested data. the data structure of the transmitted monitor message depends on the device which is programmed. therefore the first byte of the message is a specific address code which contains in the higher nibble a monitor channel address to identify different devices. the length of the messages depends on the accessed device and the type of monitor command. the siuc does not support monitor channel slave mode. 5.5.4.4 monitor time-out procedure to prevent lock-up situations in a monitor transmission a time-out procedure can be enabled by setting the time-out bit (tout) in the monitor configuration register (mconf). an internal timer is always started when the transmitter must wait for the reply of the addressed device. after 5 ms without reply the timer expires and the transmission will be aborted with a eom (end of message) command by setting the mx bit to ? 1 ? for two consecutive iom-2 frames. mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_norm.vsd 8 psb 2154 isdn module data sheet 184 2001-01-24 5.5.4.5 monitor interrupt logic figure 92 shows the monitor interrupt structure of the siuc-x. the monitor data receive interrupt status mdr has two enable bits, monitor receive interrupt enable ( mre ) and mr bit control ( mrc ). the monitor channel end of reception mer , monitor channel data acknowledged mda and monitor channel data abort mab interrupt status bits have a common enable bit monitor interrupt enable mie . mre prevents the occurrence of mdr status, including when the first byte of a packet is received. when mre is active (1) but mrc is inactive, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are active, mdr is always generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. (additionally, an active mrc enables the control of the mr handshake bit according to the monitor channel protocol.) the monitor status interrupt in ista can be masked in the ien1 register. figure 92 monitor interrupt structure st icb mos tran icd cic wov interrupt ista ien1 mos mre mdr mie mda mer mab mosr mocr ica psb 2154 isdn module data sheet 185 2001-01-24 5.5.5 c/i channel handling the command/indication channel carries real-time status information between the siuc-x and another device connected to the iom-2 interface. 1) one c/i channel (called c/i0) conveys the commands and indications between the layer-1 and the layer-2 parts of the siuc-x. it can be accessed by an external layer-2 device e.g. to control the layer-1 activation/deactivation procedures. c/i0 channel access may be arbitrated via the tic bus access protocol. in this case the arbitration is done in iom-2 channel 2 (see figure 72 ). the c/i0 channel is accessed via register cir0 (in receive direction, layer-1 to layer-2) and register cix0 (in transmit direction, layer-2 to layer-1). the c/i0 code is four bits long. a listing and explanation of the layer-1 c/i codes can be found in chapter 5.3.2 . in the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated anytime a change occurs (ista.cic). a new code must be found in two consecutive iom-2 frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cix0 is continuously transmitted in c/i0. 2) a second c/i channel (called c/i1) can be used to convey real time status information between the siuc-x and various non-layer-1 peripheral devices e.g. psb 2161 arcofi-ba. the c/i1 channel consists of four or six bits in each direction.the width can be changed from 4bit to 6bit by setting bit cix1.cicw. in 4-bit mode 6-bits are written whereby the higher 2 bits must be set to ? 1 ? and 6-bits are read whereby only the 4 lsbs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). the c/i1 channel is accessed via registers cir1 and cix1. a change in the received c/i1 code is indicated by an interrupt status without double last look criterion. cic interrupt logic figure 93 shows the cic interrupt structure. a cic interrupt may originate ? from a change in received c/i channel 0 code (cic0) or ? from a change in received c/i channel 1 code (cic 1). the two corresponding status bits cic0 and cic1 are read in cir0 register. cic1 can be individually disabled by clearing the enable bit ci1e in the cix1 register. in this case the occurrence of a code change in cir1 will not be displayed by cic1 until the corresponding enable bit has been set to one. bits cic0 and cic1 are cleared by a read of cir0. an interrupt status is indicated every time a valid new code is loaded in cir0 or cir1. psb 2154 isdn module data sheet 186 2001-01-24 the cir0 is buffered with a fifo size of two. if a second code change occurs in the received c/i channel 0 before the first one has been read, immediately after reading of cir0 a new interrupt will be generated and the new code will be stored in cir0. if several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. for cir1 no fifo is available. the actual code of the received c/i channel 1 is always stored in cir1. figure 93 cic interrupt structure st icb mos tran icd cic wov interrupt ista ien2 cic1 ci1e cic0 cir0 cix1 ica cic psb 2154 isdn module data sheet 187 2001-01-24 5.5.6 d-channel access control d-channel access control is defined to guarantee all connected tes and hdlc controllers a fair chance to transmit data in the d-channel. collisions are possible on the iom-2 interface if there is more than one hdlc controller connected or on the s-interface when there is more than one terminal connected in a point to multipoint configuration (nt te1 ? te8). both arbitration mechanisms are implemented in the siuc-x and will be described in the following two chapters. 5.5.6.1 stop/go bit handling the two d-channel access procedures are handled via the stop/go bit handling described in this chapter. the availability of the s/t interface d channel is indicated in bit 5 "stop/go" (s/g) of the last octet in dd channel 2 ( figure 94 ). s/g = 1 : stop s/g = 0 : go the stop/go bit is available to other layer-2 devices connected to the iom-2 interface to determine if they can access the s/t bus d channel in upstream direction. figure 94 structure of last octet of ch2 on dd the s/g bit can also be output on pin aux7/sgo (stop/go bit output is auxiliary function of pin aux7). in this case the sgo signal changes with the d-bits of the iom channel. the signal length depends on tr_conf2.sgd and the polarity is selected via tr_conf2.sgp. itd09693 d ci1 mon1 ic2 ic1 ci0 mon0 b2 b1 mr mx mx mr s/g a/b a/b s/g stop/go available/blocked dd e e psb 2154 isdn module data sheet 188 2001-01-24 5.5.6.2 tic bus d-channel access control the tic bus is imlemented to organize the access to the layer-1 functions provided in the siuc-x (c/i-channel) and to the d-channel from up to 7 external communication controllers (see figure 95 ). to this effect the outputs of the d-channel controllers (e.g. icc - isdn communication controller peb 2070) are wired-or (negative logic, i.e. a ? 0 ? wins) and connected to pin du. the inputs of the iccs are connected to pin dd. external pull-up resistors on du/ dd are required. the arbitration mechanism must be activated by setting moded.dim2- 0=00x. figure 95 applications of tic bus in iom-2 bus configuration the arbitration mechanism is implemented in the last octet in iom-2 channel 2 of the iom-2 interface (see figure 96 ). an access request to the tic bus may either be generated by software (p access to the c/i channel) or by the siuc-x itself (transmission of an hdlc frame in the d-channel). a software access request to the bus is effected by setting the bac bit (cix0 register) to ? 1 ? . in the case of an access request, the siuc-x checks the bus accessed-bit bac (bit 5 of last octet of ch2 on du, see figure 96 ) for the status "bus free ? , which is indicated by a logical ? 1 ? . if the bus is free, the siuc-x transmits its individual tic bus address tad programmed in the cix0 register (cix0.tba2-0). the siuc-x sends its tic bus address tad and compares it bit by bit with the value on du. if a sent bit set to ? 1 ? is read back as ? 0 ? because of the access of another d-channel source with a lower tad, the siuc- x withdraws immediately from the tic bus, i.e. the remaining tad bits are not 2154_67.vsd icc (7) icc (2) icc (0) . . . d-channel control s- transceiver siuc nt tic-bus on iom-2 s-interface u-interface psb 2154 isdn module data sheet 189 2001-01-24 transmitted. the tic bus is occupied by the device which sends its address error-free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. this one will set bac=0 on tic bus and starts d-channel transmission in the same frame. figure 96 structure of last octet of ch2 on du when the tic bus is seized by the siuc-x, the bus is identified to other devices as occupied via the du ch2 bus accessed-bit state ? 0 ? until the access request is withdrawn. after a successful bus access, the siuc-x is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. if none of the devices connected to the iom-2 interface request access to the d and c/ i channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i channels. note: bit bac (cix0 register) should be reset by the p when access to the c/i channels is no more requested, to grant other devices access to the d and c/i channels. du psb 2154 isdn module data sheet 190 2001-01-24 5.5.6.3 s-bus priority mechanism for d-channel the s-bus access procedure specified in itu i.430 was defined to organize d-channel access with multiple tes connected to a single s-bus (see figure 97 ). to implement collision detection the d (channel) and e (echo) bits are used. the d- channel s-bus condition is indicated towards the iom-2 interface with the s/g bit (see above). the access to the d-channel is controlled by a priority mechanism which ensures that all competing tes are given a fair access chance. this priority mechanism discriminates among the kind of information exchanged and information exchange history: layer-2 frames are transmitted in such a way that signalling information is given priority (priority class 1) over all other types of information exchange (priority class 2). furthermore, once a te having successfully completed the transmission of a frame, it is assigned a lower level of priority of that class. the te is given back its normal level within a priority class when all tes have had an opportunity to transmit information at the normal level of that priority class. the priority mechanism is based on a rather simple method: a te not transmitting layer- 2 frames sends binary 1s on the d-channel. as layer-2 frames are delimited by flags consisting of the binary pattern ? 01111110 ? and zero bit insertion is used to prevent flag imitation, the d-channel may be considered idle if more than seven consecutive 1s are detected on the d-channel. hence by monitoring the d echo channel, the te may determine if the d-channel is currently used by another te or not. a te may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. this number is fixed to 8 in priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and 11 for class 2. a te, when in the active condition, is monitoring the d-echo channel (e-bits), counting the number of consecutive binary 1s. if a 0 bit is detected, the te restarts counting the number of consecutive binary 1s. if the required number of 1s according to the actual level of priority has been detected, the te may start transmission of an hdlc frame. if a collision occurs, the te immediately shall cease transmission, return to the d-channel monitoring state, and send 1s over the d-channel. psb 2154 isdn module data sheet 191 2001-01-24 figure 97 d-channel access control on the s-interface the above described priority mechanism is fully implemented in the transceiver. for this purpose the d-channel collission detection according to itu i.430 must be enabled by setting moded.dim2-0 to ? 0x1 ? . in this case the transceiver continuously compares the received e-echo bits with its own transmitted d data bits. depending on the priority class selected, 8 or 10 consecutive ones (high priority level) need to be detected before the transceiver sends valid d-channel data on the upstream d-bits on s. in low priority level 9 or 11 consecutive ones are required. the transceiver controls the s/g bit on iom-2 in a way that internal delays in the transceiver path are compensated, i.e. the s/g is set to 0 ( ? go ? ) before the required number of ones is counted. due to that reason d-channel bits in the transceiver transmit path must be discarded and the s/g bit must be set to ? 1 ? if a collision on s is detected. the priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the command/indication (c/i) channel of the iom-2 interface to the transceiver. if the activation is initiated by a te, the priority class is selected implicitly by the choice of the activation command. if the s-interface is activated from the nt, an activation command selecting the desired priority class should be programmed at the te on reception of the activation indication (ai8 or ai10). in the activated state the priority class may be changed whenever required by simply programming the desired activation request command (ar8 or ar10). 21150_10 d-channel control s- transceiver d-channel control s- transceiver ipac-x nt s-interface d-bits d-channel control s- transceiver e-bits u-interface . . . te 1 te 2 te 8 psb 2154 isdn module data sheet 192 2001-01-24 5.5.6.4 state machine of the d-channel arbiter figure 98 gives a simplified view of the state machine of the d-channel arbiter. cnt is the number of ? 1 ? on the iom-2 d-channel and bac corresponds to the bac-bit on iom- 2. the number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). figure 98 state machine of the d-channel arbiter (simplified view) note: the figure above provides a simplified view only. if the s-transceiver is reset by sres.res_s = ? 1 ? or disabled by tr_conf0.dis_tr = ? 1 ? , then the d-channel arbiter is in state ready (s/g = ? 1 ? ), too. the s/g evaluation of the hdlc controller has to be disabled in this case; otherwise, the hdlc is not able to send data. 1. local d-channel controller transmits upstream in the initial state ( ? ready ? state) neither the local d-channel sources nor any of the terminals connected to the s-bus transmit in the d-channel. the s-transceiver thus receives bac = ? 1 ? (iom-2 du line) and transmits s/g = ? 1 ? (iom-2 dd line). the access will then be established according to the following procedure: bac=1& dci=0 ready s/g = 1 e=d 1)2) rst=0, a/b=0, mode=0xx d-channel_arbitration.vsd bac = d.c. dci = 0 saccess s/g = 1 e = d 1) &cnt n (bac=0 or dci=1) (bac=1 & dci=0) cnt 6 (cnt 2&d=0) & [bac = 1 or (bac = 0 & cnt < n)] 1) setting dci = 1 causes e = d 2) setting a/b = 0 causes e = d bac = 0 or dci = 1 local access wait for start flag s/g = 0 e=d cnt = 6 bac = d.c. dci = d.c. local access transmit/stopflag s/g = 0 e=d bac dci state s/g e in out psb 2154 isdn module data sheet 193 2001-01-24 local d-channel source verifies that bac bit is set to one (currently no bus access). local d-channel source issues tic bus address and verifies that no controller with higher priority requests transmission (tic bus access must always be performed even if no other d-channel sources are connected to iom-2). local d-channel source issues bac = ? 0 ? to block other sources on iom-2 and to announce d-channel access. s-transceiver pulls s/g bit to zero ( ? local access ? state) as soon as cnt n (see note) to allow for further d-channel access. s-transceiver transmits inverted echo channel (e bits) on the s-bus to block all connected s-bus terminals (e = d ). blocking the s-bus by inverting the d-bits in the echo channel (e = d ) can be enforced by the host via tr_mode.dch_inh = 1 and/or any project specific pin signal like dci. local d-channel source commences with d data transmission on iom-2 as long as it receives s/g = ? 0 ? . after d-channel data transmission is completed the controller sets the bac bit to one. s-transceiver transmits non-inverted echo (e = d). s-transceiver pulls s/g bit to one ( ? ready ? state) to block the d-channel controller on iom-2. note: if right after d-data transmission the d-channel arbiter goes to state ? ready ? and the local d-channel source wants to transmit again, then it may happen that the leading ? 0 ? of the start flag is written into the d-channel before the d-channel source recognizes that the s/g bit is pulled to ? 1 ? and stops transmission. in order to prevent unintended transitions to state ? s-access ? , the additional condition cnt 2 is introduced. as soon as cnt n, the s/g bit is set to ? 0 ? and the d-channel source may start transmission again (if tic bus is occupied). this allows an equal access for d-channel sources on iom-2 and on the s interface. 2. terminal transmits d-channel data upstream the initial state is identical to that described in the last paragraph. when one of the connected s-bus terminals needs to transmit in the d-channel, access is established according to the following procedure: s-transceiver recognizes that the d-channel on the s-bus is active via d = ? 0 ? . s-transceiver transfers s-bus d-channel data transparently through to the upstream iom-2 bus. psb 2154 isdn module data sheet 194 2001-01-24 5.5.7 activation/deactivation of iom-2 interface the iom-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. in this deactivated state is fsc = ? 1 ? , dcl and bcl = ? 0 ? and the data lines are ? 1 ? . the iom-2 interface can be kept active while the s interface is deactivated by setting the cfs bit to "0" (mode1 register). this is the case after a hardware reset. if the iom-2 interface should be switched off while the s interface is deactivated, the cfs bit should be set to ? 1 ? . in this case the internal oscillator is disabled when no signal (info 0) is present on the s bus and the c/i command is ? 1111 ? = diu. if the te wants to activate the line, it has first to activate the iom-2 interface either by using the "software power up" function (iom_cr.spu bit) or by setting the cfs bit to "0" again. the deactivation procedure is shown in figure 99 . after detecting the code diu (deactivate indication upstream) the layer 1 of the siuc-x responds by transmitting did (deactivate indication downstream) during subsequent frames and stops the timing signals synchronously with the end of the last c/i (c/i0) channel bit of the fourth frame. figure 99 deactivation of the iom-2 interface the clock pulses will be enabled again when the du line is pulled low (bit spu in the iom_cr register), i.e. the c/i command tim = "0000" is received by layer 1, or when a non-zero level on the s-line interface is detected (if tr_conf0.ldd=0). the clocks are turned on after approximately 0.2 to 4 ms depending on the oscillator. iom ? -2 deactivated dc dc dc dc di di di di di di di di di b1 b2 d cio d cio dcl dd du fsc iom ? -2 itd09655_s.vsd dr dr dr dr dr psb 2154 isdn module data sheet 195 2001-01-24 dcl is activated such that its first rising edge occurs with the beginning of the bit following the c/i (c/i0) channel. after the clocks have been enabled this is indicated by the pu code in the c/i channel and, consequently, by a cic interrupt. the du line may be released by resetting the software power up bit iom_cr = ? 0 ? and the c/i code written to cix0 before (e.g. tim or ar8) is output on du. the siuc-x supplies iom-2 timing signals as long as there is no diu command in the c/i (c/i0) channel. if timing signals are no longer required and activation is not yet requested, this is indicated by programming diu in the cix0 register. figure 100 activation of the iom-2 interface itd09656 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ fsc du dd fsc du dd dcl spu = 1 spu = 0 cic : cixo = tim int. tim pu b1 b1 mx mr 0.2 to 4 ms 132 x dcl tim tim pu pu pu pu r iom -ch1 r iom -ch2 iom -ch2 r iom r -ch1 psb 2154 isdn module data sheet 196 2001-01-24 5.6 hdlc controllers the siuc-x contains three hdlc controllers which can arbitrarily be used for the layer-2 functions of the d- channel protocol (lapd) and b-channel protocols. by setting the enable hdlc channel bits (en_d, en_b1h, en_b2h) in the dci_cr/bch_cr registers each of the hdlc controllers can access the d or b-channels or any combination of them e.g. 18 bit idsl data (2b+d). they perform the framing functions used in hdlc based communication: flag generation/recognition, bit stuffing, crc check and address recognition. the d-channel fifo has a size of 64 byte per direction. each of the two b-channel fifos has a size of 128 bytes per direction. they are implemented as cyclic buffers. the transceiver reads and writes data sequentially with constant data rate whereas the data transfer between fifo and microcontroller uses a block oriented protocol with variable block sizes. the configuration, control and status bits related to the hdlc controllers are all assigned to the following address ranges: note: for b-channel data access a single address location is used to read from and write to the fifo. for d-channel access the address range 00 h -1f h is used (similar as in isac-s peb 2086), however a single address from this range is sufficient to access the fifo as the internal fifo pointer is incremented automatically independent from the external address. the mechanisms for access to the fifos are identical for d- and b-channels, therefore the following description applies to both of them and for simplification specific references like registers are indicated by an ? x ? (stands for ? d ? and ? b ? ) to indicate it is relevant for d- and b-channel (e.g. istax means istad/istab). table 25 hdlc controller address range fifo address config/ctrl/status registers d-channel 00 h -1f h 20 h -29 h b-channel a 7a h 70 h -79 h b-channel b 8a h 80 h -89 h psb 2154 isdn module data sheet 197 2001-01-24 5.6.1 message transfer modes the hdlc controllers can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus the receive data flow and the address recognition features can be programmed in a flexible way to satisfy different system requirements. the structure of a d-channel two-byte address (lapd) is shown below: for address recognition on the d-channel the siuc-x contains four programmable registers for individual sapi and tei values (sap1, 2 and tei1, 2), plus two fixed values for the ? group ? sapi (sapg = ? fe ? or ? fc ? ) and tei (teig = ? ff ? ). the received c/r bit is excluded from the address comparison. ea is the address field extension bit which must be set to ? 1 ? according to hdlc lapd. the structure of a b-channel two-byte address is as follows: for address recognition on the b-channel the siuc-x contains four programmable registers for individual receive address high and low values (rah1, 2 and ral1, 2), plus two fixed values for the high address byte (group address = ? fe ? or ? fc ? ) and one fixed value for the low address byte (group address = ? ff ? ). the received c/r bit is excluded from the address comparison. ea is the address field extension bit which must be set to ? 1 ? according to hdlc lapd. high address byte low address byte sapi1, 2, sapg c/r 0 tei 1, 2, teig ea high address byte low address byte rah1, 2, group address c/r 0 ral1, 2, group address psb 2154 isdn module data sheet 198 2001-01-24 operating modes there are 5 different operating modes which can be selected via the mode selection bits mds2-0 in the modex registers: non-auto mode (mds2-0 = ? 01x ? ) characteristics: full address recognition with one-byte (mds = ? 010 ? ) or two-byte (mds = ? 011 ? ) address comparison all frames with valid addresses are accepted and the bytes following the address are transferred to the p via rfifox. additional information is available in rstax. transparent mode 0 (mds2-0 = ? 110 ? ). characteristics: no address recognition every received frame is stored in rfifox (first byte after opening flag to crc field). additional information can be read from rstax. transparent mode 1 (mds2-0 = ? 111 ? ). characteristics: sapi recognition (d-channel) high byte address recognition (b-channel) a comparison is performed on the first byte after the opening flag with sap1, sap2 and ? group ? sapi (fe h /fc h ) for d-channel, and with rah1, rah2 and group address (fe h / fc h ) for b-channel. in the case of a match, all the following bytes are stored in rfifox. additional information can be read from rstax. transparent mode 2 (mds2-0 = ? 101 ? ). characteristics: tei recognition (d-channel) low byte address recognistion (b-channel) a comparison is performed only on the second byte after the opening flag, with tei1, tei2 and group tei (ff h ) for d-channel, and with ral1 and ral2 for b-channel. in case of a match the rest of the frame is stored in the rfifox. additional information is available in rstax. extended transparent mode (mds2-0 = ? 100 ? ). characteristics: fully transparent in extended transparent mode fully transparent data transmission/reception without hdlc framing is performed i.e. without flag generation/recognition, crc generation/ check, bitstuffing mechanism. this allows user specific protocol variations. also refer to chapter 5.6.5 . psb 2154 isdn module data sheet 199 2001-01-24 5.6.2 data reception 5.6.2.1 structure and control of the receive fifo the cyclic receive fifo buffers with a length of 64-byte for d-channel and 128 byte for each of the two b-channels have variable fifo block sizes (thresholds) of 4, 8, 16 or 32 bytes for d-channel and 8, 16, 32 or 64 bytes for b-channels which can be selected by setting the corresponding rfbs bits in the exmx registers. the variable block size allows an optimized hdlc processing concerning frame length, i/o throughput and interrupt load. the transfer protocol between hdlc fifo and microcontroller is block oriented with the microcontroller as master. the control of the data transfer between the cpu and the siuc-x is handled via interrupts (siuc-x host) and commands (host siuc-x). there are three different interrupt indications in the istax registers concerned with the reception of data: ? rpf ( r eceive p ool f ull) interrupt, indicating that a data block of the selected length (exmx.rfbs) can be read from rfifox. the message which is currently received exceeds the block size so further blocks will be received to complete the message. ? rme ( r eceive m essage e nd) interrupt, indicating that the reception of one message is completed, i.e. either a short message is received (message length the defined block size (exmx.rfbs)) or the last part of a long message is received (message length > the defined block size (exmx.rfbs)) and is stored in the rfifox. ? rfo ( r eceive f rame o verflow) interrupt, indicating that a complete frame could not be stored in rfifox and is therefore lost as the rfifox is occupied. this occurs if the host fails to respond quickly enough to rpf/rme interrupts since previous data was not read by the host. there are two control commands that are used with the reception of data: ? rmc ( r eceive m essage c omplete) command, telling the siuc-x that a data block has been read from the rfifox and the corresponding fifo space can be released for new receive data. ? rres ( r eceiver r eset) command, resetting the hdlc receiver and clearing the receive fifo of any data (e.g. used before start of reception). it has to be used after a change of the message transfer mode. pending interrupt indications of the receiver are not cleared by rres, but have to be cleared by reading these interrupts. note: the significant interrupts and commands are underlined as only these are commonly used during a normal reception sequence. psb 2154 isdn module data sheet 200 2001-01-24 the following description of the receive fifo operation is illustrated in figure 101 for a rfifox block size (threshold) of 16 and 32 bytes. the rfifox requests service from the microcontroller by setting a bit in the istax register, which causes an interrupt (rpf, rme, rfo). the microcontroller then reads status information (rbchx,rbclx), data from the rfifox and then may change the receive fifo block size (exmx.rfbs). a block transfer is completed by the microcontroller via a receive message complete (cmdrx.rmc) command. this causes the space of the transferred bytes being released for new data and in case the frame was complete (rme) the reset of the receive byte counter rbc (rbchx,rbclx). the total length of the frame is contained in the rbchx and rbclx registers which contain a 12 bit number (rbc11...0), so frames up to 4095 byte length can be counted. if a frame is longer than 4095 bytes, the rbch.ov (overflow) bit will be set. the least significant bits of rbclx contain the number of valid bytes in the last data block indicated by rmex (length of last data block selected block size). table 26 shows which rbc bits contain the number of bytes in the last data block or number of complete data blocks respectively. if the number of bytes in the last data block is ? 0 ? the length of the last received block is equal to the block size. table 26 receive byte count with rbc11...0 in the rbchx/rbclx registers exmd1.rfbs bits (d-channel) exmb.rfbs bits (b-channel) selected block size number of complete data blocks in bytes in the last data block in -- ? 00 ? 64 byte rbc11...6 rbc5...0 ? 00 ?? 01 ? 32 byte rbc11...5 rbc4...0 ? 01 ?? 10 ? 16 byte rbc11...4 rbc3...0 ? 10 ?? 11 ? 8 byte rbc11...3 rbc2...0 ? 11 ? -- 4 byte rbc11...2 rbc1...0 psb 2154 isdn module data sheet 201 2001-01-24 the transfer block size (exmx.rfbs) is 32 bytes for d-channel and 64 bytes for b- channel by default. if it is necessary to react to an incoming frame within the first few bytes the microcontroller can set the rfifox block size to a smaller value. each time a cmdrx.rmc or cmdrx.rres command is issued, the rfifox access controller sets its block size to the value specified in exmr.rfbs, so the microcontroller has to write the new value for rfbs before the rmc command. when setting an initial value for rfbs before the first hdlc activities, a rres command must be issued afterwards. the rfifox can hold any number of frames fitting in the 64 bytes (d-channel)/128 bytes (b-channel) independent of rfbs (but the rfifo is read blockwise according to the selected threshold). at the end of a frame, the rstax byte is always appended. all generated interrupts are inserted together with all additional information into a wait line to be individually passed to the host. for example if several data blocks have been received to be read by the host and the host acknowledges the current block, a new rpf or rme interrupt from the wait line is immediately generated to indicate new data. psb 2154 isdn module data sheet 202 2001-01-24 figure 101 rfifo operation hdlc receiver 32 16 8 4 rpf rfifo p rbc=4h ram hdlc receiver rfifo access controller 32 16 8 4 rfbs=01 ram exmx.rfbs=01 rmc exmx.rfbs=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt istax.rpf the p has read the 4 bytes, sets rfbs=01 (16 bytes) and completes the block transfer by an cmdrx.rmc command. following cmdrx.rmc the 4 bytes of the last block are deleted. rfacc rfacc is set. rfifo access controller rfbs=11 hdlc receiver 32 16 8 rpf rfifo p rbc=14h ram rsta rsta rsta the hdlc receiver has written further data into the fifo. when a frame is complete, a status byte (rstax) is appended. when the rfacc detects 16 valid bytes, it sets an rpf interrupt. the p reads the 16 bytes hdlc receiver 32 16 8 rme rfifo rbc=16h ram rsta rsta rsta after the rmc acknowledgement the the frame, therefore it asserts an rme interupt and increments the rbc counter by 2. rmc rfacc rfacc meanwhile two more short frames have been received. and acknowledges the transfer by setting cmdrx.rmc. this causes the space occupied by the 16 bytes being released. p rfifo access controller rfbs=01 rfifo access controller rfbs=01 rfacc detects an rsta byte, i.e. end of psb 2154 isdn module data sheet 203 2001-01-24 possible error conditions during reception of frames if parts of a frame get lost because the receive fifo is full, the receive data overflow (rdo) byte in the rstax byte will be set. if a complete frame is lost, i.e. if the fifo is full when a new frame is received, the receiver will assert a receive frame overflow (rfo) interrupt. the microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it reads the same data again and again. on the other hand, if it doesn ? t read or doesn ? t want to read all data, they are deleted anyway after the rmc command. if the microcontroller reads data without a prior rme or rpf interrupt, the content of the rfifox would not be corrupted, but new data is only transferred to the host as long as new valid data is available in the rfifox, otherwise the last data is read again and again. the general procedures for a data reception sequence are outlined in the flow diagram in figure 102 . psb 2154 isdn module data sheet 204 2001-01-24 figure 102 data reception procedures xx hdlc_rflow.vsd start receive message end rme ? receive pool full rpf ? read counter rd_count := rfbs or rd_count := rbc read rd_count bytes from rfifo receive message complete write rmc change block size write exmr.rfbs (optional) read rbc rd_count := rbc y y n n * 1) rbc = rbch + rbcl register rfbs: refer to exmr register in case of rme the last byte in rfifo contains the receive status information rsta * 1) psb 2154 isdn module data sheet 205 2001-01-24 figure 103 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. the fifo threshold (block size) is set to 32 byte in this example: after 32 byte of frame 1 have been received an rpf interrupt is generated to indicate that a data block can be read from the rfifox. the host reads the first data block from rfifox and acknowledges the reception by rmc. meanwhile the second data block is received and stored in rfifox. the second 32 byte block is indicated by rpf which is read and acknowledged by the host as described before. the reception of the remaining 4 bytes plus rstax are indicated by rme (i.e. the receive status is always appended to the end of the frame). the host gets the number of bytes (count = 5) from rbclx/rbchx and reads out the rfifox and optionally the status register rsta. the frame is acknowledged by rmc. the second frame is received and indicated by rme interrupt. the host gets the number of bytes (count = 13) from rbclx/rbchx and reads out the rfifox and optionally the status register. the rfifox is acknowledged by rmc. the third frame is transferred in the same way. figure 103 reception sequence example fifoseq_rec.vsd * 1) the last byte contains the receive status information psb 2154 isdn module data sheet 206 2001-01-24 5.6.2.2 receive frame structure the management of the received hdlc frames as affected by the different operating modes (see chapter 5.6.1 ) is shown in figure 104 . figure 104 receive data flow i 21150_13 addr flag ctrl crc flag address control data status rstax rfifox *1) sap1 sap2 sapg *2) tei1 tei2 teig *2) rah1 rah2 gr.adr. *2) ral1 ral2 gr.adr. *2) d-channel b-channel non auto/16 mode 011 mds2 mds1 mds0 rfifox ral1 ral2 *2) _ *3) d-channel b-channel non auto/8 010 tei1 tei2 *2) _ *3) rfifox transparent 0 110 rfifox 111 transparent 1 sap1 sap2 sapg *2) rah1 rah2 gr.adr. *2) d-channel b-channel rfifox tei1 tei2 teig *2) ral1 ral2 *2) 101 d-channel b-channel transparent 2 compared with registers (d- or b-channel) description of symbols: stored in fifo/registers *1) crc optionally stored in rfifox if exmx:rcrc=1 *2) address optionally stored in rfifox if exmx:sra=1 *3) start of the control field in case of an 8 bit address *4) content of rsta register appended at the frameend into rfifox *4) rstax *1) *4) rstax *1) *4) rstax *1) *4) rstax *1) *4) psb 2154 isdn module data sheet 207 2001-01-24 the siuc-x indicates to the host that a new data block can be read from the rfifox by means of an rpf interrupt (see previous chapter). user data is stored in the rfifox and information about the received frame is available in the rbclx and rbchx registers and the rstax bytes which are listed in table 27 . the rstax register is always appended in the rfifox as last byte to the end of a frame. table 27 receive information at rme interrupt information register bit mode type of frame (command/ response) rstax c/r non-auto mode, 2-byte address field transparent mode 1 recognition of sapi rstad rstab sa1, 0 ha1, 0 non-auto mode, 2-byte address field transparent mode 1 recognition of tei rstad rstab ta la all except transparent mode 0 result of crc check (correct/incorrect) rstax crc all valid frame rstax vfr all abort condition detected (yes/no) rstax rab all data overflow during reception of a frame (yes/no) rstax rdo all number of bytes received in rfifo rbcl rbc4-0 all (also see table 26 ) message length rbclx rbchx rbc11-0 all rfifo overflow rbchx ov all psb 2154 isdn module data sheet 208 2001-01-24 5.6.3 data transmission 5.6.3.1 structure and control of the transmit fifo the cyclic transmit fifo buffers with a length of 64-byte for d-channel and 128 byte for each of the two b-channels have variable fifo block sizes (thresholds) of 16 or 32 bytes for d-channel and 32 or 64 bytes for b-channels which can be selected by setting the corresponding xfbs bits in the exmx registers. there are three different interrupt indications in the istax registers concerned with the transmission of data: ? xpr ( t ransmit p ool r eady) interrupt, indicating that a data block of up to 16 or 32 byte (d-channel), 32 or 64 byte (b-channel) can be written to the xfifox (block size selected via exmx.xfbs). an xpr interrupt is generated either after an xres (transmitter reset) command (which is issued for example for frame abort) or when a data block from the xfifox is transmitted and the corresponding fifo space is released to accept further data from the host. ? xdu ( t ransmit d ata u nderrun) interrupt, indicating that the transmission of the current frame has been aborted (seven consecutive ? 1 ? s are transmitted) as the xfifox holds no further transmit data. this occurs if the host fails to respond to an xpr interrupt quickly enough. ? only valid for d-channel: xmr ( t ransmit m essage r epeat) interrupt, indicating that the transmission of the complete last frame has to be repeated as a collision on the s bus has been detected and the xfifox does not hold the first data bytes of the frame (collision after the 16th/ 32nd byte or after the 32nd/64th byte of the frame, respectively). the occurence of an xdu or xmr interrupt clears the xfifox and an xmr interrupt is issued together with an xdu or xmr interrupt, respectively. data cannot be written to the xfifox as long as an xdu/xmr interrupt is pending. three different control commands are used for transmission of data: ? xtf ( t ransmit t ransparent f rame) command, telling the siuc-x that up to 16 or 32 byte (d-channel) or 32 or 64 byte (b-channel) have been written to the xfifox and should be transmitted. a start flag is generated automatically. ? xme ( t ransmit m essage e nd) command, telling the siuc-x that the last data block written to the xfifox completes the corresponding frame and should be transmitted. this implies that according to the selected mode a frame end (crc + closing flag) is generated and appended to the frame. psb 2154 isdn module data sheet 209 2001-01-24 ? xres ( t ransmitter r eset) command, resetting the hdlc transmitter and clearing the transmit fifo of any data. after an xres command the transmitter always sends an abort sequence, i.e. this command can be used to abort a transmission. pending interrupt indications of the transmitter are not cleared by xres, but have to be cleared by reading these interutps. optionally two additional status conditions can be read by the host: ? xdov ( t ransmit d ata o verflow), indicating that the data block size has been exceeded, i.e. more than 16 or 32 byte (d-channel) or 32 or 64 byte (b-channel) were entered and data was overwritten. ? xfw ( t ransmit f ifo w rite enable), indicating that data can be written to the xfifox. this status flag may be polled instead of or in addition to xpr. note: the significant interrupts and commands are underlined as only these are usually used during a normal transmission sequence. the xfifo requests service from the microcontroller by setting a bit in the istax register, which causes an interrupt (xpr, xdu, xmr). the microcontroller can then read the status register starx (xfw, xdov), write data in the fifo and it can change the transmit fifo block size (exmx.xfbs) if required. the instant of the initiation of a transmit pool ready (xpr) interrupt after different transmit control commands is listed in table 28 . when setting xme the transmitter appends the crc and the endflag at the end of the frame. when xtf & xme has been set, the xfifox is locked until successful transmission of the current frame, so a consecutive xpr interrupt also indicates successful transmission of the frame whereas after xme or xtf the xpr interrupt is asserted as soon as there is space for one data block in the xfifox. table 28 xpr interrupt (availability of xfifox) after xtf, xme commands cmdrx register transmit pool ready (xpr) interrupt initiated ... xtf as soon as the selected buffer size in the fifox is available. xtf & xme after the successful transmission of the closing flag. the transmitter always sends an abort sequence. xme as soon as the selected buffer size in the fifo is available, two consecutive frames share flags. psb 2154 isdn module data sheet 210 2001-01-24 the transfer block size is 32 bytes (for d-channel) or 64 bytes (for b-channel) by default, but sometimes, if the microcontroller has a high computational load, it is useful to increase the maximum reaction time for an xpr interrupt. the maximum reaction time is: t max = (xfifox size - xfbs) / data transmission rate with a selected block size of 16 bytes (d-channel only) an xpr interrupt indicates when a transmit fifo space of at least 16 bytes is available to accept further data, i.e. there are still a maximum of 48 bytes (64 bytes - 16 bytes) to be transmitted. with a 32 bytes block size (d- or b-channel) the xpr is initiated when a transmit fifo space of at least 32 bytes is available to accept further data, i.e. there are still a maximum of 32 bytes (d- channel: 64 bytes - 32 bytes) or 96 bytes (b-channel: 128 bytes - 32 bytes) to be transmitted. the maximum reaction time for the smaller block size is 50 % higher with the trade-off of a doubled interrupt load. with a selected block size an xpr always indicates the available space in the xfifox, so any number of bytes smaller than the selected xfbs may be stored in the fifo during one ? write block ? access cycle. similar to rfbs for the receive fifo, a new setting of xfbs takes effect after the next xtf,xme or xres command. xres resets the xfifox. the xfifox can hold any number of frames fitting in the 64 bytes (d-channel) or 128 bytes (b-channel), respectively. possible error conditions during transmission of frames if the transmitter sees an empty fifo, i.e. if the microcontroller doesn ? t react fast enough to an xpr interrupt, an xdu (transmit data underrun) interrupt will be generated. if the hdlc channel becomes unavailable during transmission the transmitter tries to repeat the current frame as specified in the lapd protocol. this is impossible after the first data block has been sent (16 or 32 bytes for d-channel; 32 or 64 byte for b-channel), in this case an xmr transmit message repeat interrupt is set and the microcontroller has to send the whole frame again. both xmr and xdu interrupts cause a reset of the xfifox. the xfifox is locked while an xmr or xdu interrupt is pending, i.d. all write actions of the microcontroller will be ignored as long as the microcontroller hasn ? t read the istax register with the set xdu, xmr interrupts. if the microcontroller writes more data than allowed (block size), then the data in the xfifox will be corrupted and the starx.xdov bit is set. if this happens, the microcontroller has to abort the transmission by cmdrx.xres and start new. the general procedures for a data transmission sequence are outlined in the flow diagram in figure 105 . psb 2154 isdn module data sheet 211 2001-01-24 figure 105 data transmission procedure 21150_25 start transmit pool ready xpr ? command xtf+xme write one data block to xfifo n y y n end of message ? end command xtf psb 2154 isdn module data sheet 212 2001-01-24 the following description gives an example for the transmission of a 76 byte frame with a selected block size of 32 byte: the host writes 32 bytes to the xfifox, issues an xtf command and waits for an xpr interrupt in order to continue with entering data. the siuc-x immediately issues an xpr interrupt (as remaining xfifox space is not used) and starts transmission. due to the xpr interrupt the host writes the next 32 bytes to the xfifox, followed by the xtf command, and waits for xpr. as soon as the last byte of the first block is transmitted, the siuc-x releases an xpr (xfifox space of first data block is free again) and continues transmitting the second block. the host writes the remaining 12 bytes of the frame to the xfifox and issues the xtf command together with xme to indicate that this is the end of frame. after the last byte of the frame has been transmitted the siuc-x releases an xpr interrupt and the host may proceed with transmission of a new frame. figure 106 transmission sequence example transmit frame 76 bytes fifoseq_tran.vsd iom interface cpu interface wr 32 bytes xtf 32 12 32 xpr xpr wr 32 bytes xtf wr 12 bytes xtf+xme xpr psb 2154 isdn module data sheet 213 2001-01-24 5.6.3.2 transmit frame structure the transmission of transparent frames (xtf command) is shown in figure 107 . for transparent frames, the whole frame including address and control field must be written to the xfifox. the host configures whether the crc is generated and appended to the frame (default) or not (selected in exmx.xcrc). further, the host selects the interframe time fill signal which is transmitted between hdcl frames (exmx.itf). one option is to send continuous flags ( ? 01111110 ? ), however if d-channel access handling (collision resolution on the s bus) is required, the signal must be set to idle (continuous ? 1 ? s are transmitted). reprogramming of itf takes effect only after the transmission of the current frame has been completed or after an xres command. figure 107 transmit data flow 5.6.4 access to iom-2 channels by setting the enable hdlc data bits (en_d, en_b1h, en_b2h) in the dci_cr register (d-channel) and in the bch_cr register (b-channel) the hdlc controller can access the d, b1 and b2 channels or any combination of them (e.g. 18 bit idsl data 2b+d). in all modes (except extended transparent mode) transmission always works frame aligned, i.e. it starts with the first selected channel, whereas reception searches for a flag anywhere in the serial data stream. flag fifoflow_tran.vsd transmit transparent frame (xtf) ctrl crc flag i address control data checkram addr * 1) xfifo * 1) the crc is generated by default. if exmr.xcrc is set no crc is appended psb 2154 isdn module data sheet 214 2001-01-24 5.6.5 extended transparent mode this non-hdlc mode is selected by setting mode2...0 to ? 100 ? . in extended transparent mode fully transparent data transmission/reception without hdlc framing is performed i.e. without flag generation/recognition, crc generation/check, bitstuffing mechanism. this allows user specific protocol variations. transmitter the transmitter sends the data out of the fifo without manipulation. transmission is always iom-2 frame aligned and byte aligned, i.e. transmission starts in the first selected channel (b1, b2, d, according to the setting of register dci_cr or bch_cr in the iom-2 handler) of the next iom-2 frame. the fifo indications and commands are the same as in other modes. if the microcontroller sets xtf & xme the transmitter responds with an xpr interrupt after sending the last byte, then it returns to its idle state (sending continuous ? 1 ? ). if the collision detection is enabled in d-channel (mode.dim = ? 0x1 ? ) the stop go bit (s/ g) can be used as clear to send indication as in any other mode. if the s/g bit is set to ? 1 ? (stop) during transmission the transmitter responds always with an xmr (transmit message repeat) interrupt. if the microcontroller fails to respond to a xpr interrupt in time and the transmitter runs out of data then it will assert an xdu (transmit data underrun) interrupt. receiver the reception is iom-2 frame aligned and byte aligned, like transmission, i.e. reception starts in the first selected channel (b1, b2, d, according to the setting of registers dci_cr and bch_cr in the iom-2 handler) of the next iom-2 frame. the fifo indications and commands are the same as in others modes. all incoming data bytes are stored in the rfifox and is additionally made available in rstax. if the fifo is full an rfo interrupt is asserted (exmx.sra = ? 0 ? ). note: in the extended transparent mode the exmx register has to be set to ? xxx00000 ? psb 2154 isdn module data sheet 215 2001-01-24 5.6.6 hdlc controller interrupts the cause of an interrupt related to the hdlc controllers is indicated in the ista register by the icd bit for d-channel, ica for b-channel a and icb for b-channel b. these bits point to the different interrupt sources of the hdlc controllers in the istad and istab registers. the individual interrupt sources of the hdlc controllers during reception and transmission of data are explained in chapter 5.6.2.1 or chapter 5.6.3.1 respectively. figure 108 interrupt status registers of the hdlc controllers each interrupt source in the istad and istab registers can selectively be masked by setting the corresponding bit in maskd/maskb to ? 1 ? . ica icd mos tran aux cic st icb ica istab xdu xpr rfo rpf rme xdu xpr rfo rpf rme xdu xpr rfo rpf rme xdu xpr rfo rpf rme maskb xdu xmr xpr rfo rpf rme maskd xdu xmr xpr rfo rpf rme istad ien1 ista 2154_33 interrupt istab maskb b-channel a b-channel b d-channel icb ien2 icd ien1 psb 2154 isdn module data sheet 216 2001-01-24 5.7 test functions the siuc-x provides test and diagnostic functions for the s-interface, the d-channel and each of the two b-channels: digital loop via tlp (test loop, tmd and tmb registers) command bit ( figure 109 ): the tx path of layer 2 is internally connected with the rx path of layer 2. the output from layer 1 (s/t) on dd is ignored. this is used for testing siuc-x functionality excluding layer 1 (loopback between xfifox and rfifox). figure 109 layer 2 test loops test of layer-2 functions while disabling all layer-1 functions and pins associated with them (including clocking) via bit tr_conf0.dis_tr. the hdlc controllers can still operate via iom-2. dcl and fsc pins become input. tmx.tlp = ? 1 ? tmx.tlp = ? 0 ? psb 2154 isdn module data sheet 217 2001-01-24 loop at the analog end of the s interface; transmission of special test signals on the s/t interface according to the modified ami code are initiated via a c/i command written in cix0 register. test loop 3 is activated with the c/i channel command activate request loop (arl). an s interface is not required since info3 is looped back internally to the receiver. when the receiver has synchronized itself to this signal, the message "test indication" (or "awake test indication") is delivered in the c/i channel. no signal is transmitted over the s interface. in the test loop mode the s interface awake detector is enabled, i.e. if a level is detected (e.g. info 2/info 4) this will be reported by the resynchronization indication (rsy). the loop function is not effected by this condition and the internally generated 192-khz line clock does not depend on the signal received at the s interface. two kinds of test signals may be sent by the siuc-x: ? single pulses and ? continuous pulses. the single pulses are of alternating polarity, one s interface bit period wide, 0.25 ms apart, with a repetition frequency of 2 khz. single pulses can be sent in all applications. the corresponding c/i command in te, lt-s and lt-t applications is tm1. continuous pulses are likewise of alternating polarity, one s-interface bit period wide, but they are sent continuously. the repetition frequency is 96 khz. continuous pulses may be transmitted in all applications. this test mode is entered in lt-s, lt-t and te applications with the c/i command tm2. psb 2154 isdn module data sheet 218 2001-01-24 5.8 isdn register description the register mapping of the siuc-x is shown in figure 110 . all addresses mentioned must be prefixed by f8 h to correspond to the isdn address space f800 h - f8ff h . figure 110 register mapping of the siuc-x the register address range from 00 h -2f h is assigned to the d-channel hdlc controller and the c/i-channel handler. the register set ranging from 30 h -3f h pertains to the transceiver and auxiliary interface registers. 21150_04 b-channel a b-channel b d- and c/i-channel iom-2 and monitor handler (not used) 80h 00h 40h 30h 70h ffh 90h transceiver, auxiliary interface 60h interrupt, general configuration isdn registers 0000h f800h f900h ffffh psb 2154 isdn module data sheet 219 2001-01-24 the address range from 40 h -5b h is assigned to the iom handler with the registers for timeslot and data port selection (tsdp) and the control registers (cr) for the transceiver data (tr), monitor data (mon), hdlc/ci data (hci) and controller access data (cda), serial data strobe signal (sds), iom interface (iom) and synchronous transfer interrupt (sti). the address range from 5c h -5f h pertains to the monitor handler. general interrupt and configuration registers are contained in the address range 60 h -65 h . the address range 70 h -8f h is assigned to the two b-channel fifos and hdlc controllers having an identical set of registers. the register summaries of the siuc-x are shown in the following tables containing the abbreviation of the register name and the register bits, the register address, the reset values and the register type (read/write). a detailed register description follows these register summaries. the register summaries and the description are sorted in ascending order of the register address. psb 2154 isdn module data sheet 220 2001-01-24 d-channel hdlc, c/i-channel handler name76543210addrr/wres rfifod d-channel receive fifo 00 h - 1f h r xfifod d-channel transmit fifo 00 h - 1f h w istad rme rpf rfo xpr xmr xdu 0 0 20 h r10 h maskd rme rpf rfo xpr xmr xdu 1 1 20 h wff h stard xdov xfw 0 0 raci 0 xaci 0 21 h r40 h cmdrd rmc rres 0 sti xtf 0 xme xres 21 h w00 h moded mds2 mds1 mds0 0 rac dim2 dim1 dim0 22 h r/w c0 h exmd1 xfbs rfbs sra xcrc rcrc 0 itf 23 h r/w 00 h timr2 cnt value 24 h r/w 00 h sap1 sapi1 0 mha 25 h wfc h sap2 sapi2 0 mla 26 h wfc h rbcld rbc7 rbc0 26 h r00 h rbchd 0 0 0 ov rbc11 rbc8 27 h r00 h tei1 tei1 ea1 27 h wff h tei2 tei2 ea2 28 h wff h rstad vfr rdo crc rab sa1 sa0 c/r ta 28 h r0f h tmd 0000000tlp29 h r/w 00 h reserved 2a-2d h cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h cir1 codr1 cicw ci1e 2f h rfe h psb 2154 isdn module data sheet 221 2001-01-24 cix1 codx1 cicw ci1e 2f h wfe h transceiver, auxiliary interface name 7 6 5 4 3 2 1 0 addr r/wres tr_ conf0 dis_ tr 0en_ icv 0 l1sw 0 exlp ldd 30 h r/w 01 h tr_ conf1 0rpll_ adj en_ sfsc 00xx x31 h r/w tr_ conf2 dis_ tx pds 0 rlp 0 0 sgp sgd 32 h r/w 80 h tr_sta rinf 0 icv 0 fsyn 0 ld 33 h r00 h tr_cmd xinf dprio tddis pd lp_a 0 34 h r/w 08 h sqrr1 msyn mfen 0 0 sqr11sqr12sqr13sqr14 35 h r40 h sqxr1 0 mfen 0 0 sqx11sqx12sqx13 sqx14 35 h w4f h sqrr2 sqr21sqr22sqr23sqr24sqr31sqr32sqr33sqr34 36 h r00 h reserved 36 h w sqrr3 sqr41sqr42sqr43sqr44sqr51sqr52sqr53sqr54 37 h r00 h reserved 37 h w istatr 0 x x x ld ric sqc sqw 38 h r00 h masktr 1 1 1 1 ld ric sqc sqw 39 h r/w ff h tr_ mode 0 0 0 0 dch_ inh mode 2 mode 1 mode 0 3a h r/w 00 h reserved 3b h acfg1 od7 od6 od5 od4 od3 od2 od1 od0 3c h r/w 00 h acfg2 a7sel a5sel fbs a4sel acl led el2 el1 3d h r/w 00 h psb 2154 isdn module data sheet 222 2001-01-24 aoe oe7oe6oe5oe4oe3oe2oe1oe0 3e h r/w ff h arx ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 3f h r atx at7 at6 at5 at4 at3 at2 at1 at0 3f h w00 h iom handler (timeslot , data port selection, cda data and cda control register) name 76543210addrr/wres cda10 controller data access register (ch10) 40 h r/w ff h cda11 controller data access register (ch11) 41 h r/w ff h cda20 controller data access register (ch20) 42 h r/w ff h cda21 controller data access register (ch21) 43 h r/w ff h cda_ tsdp10 dps 0 0 tss 44 h r/w 00 h cda_ tsdp11 dps 0 0 tss 45 h r/w 01 h cda_ tsdp20 dps 0 0 tss 46 h r/w 80 h cda_ tsdp21 dps 0 0 tss 47 h r/w 81 h bcha_ tsdp_ bc1 dps 0 0 tss 48 h r/w 80 h bcha_ tsdp_ bc2 dps 0 0 tss 49 h r/w 81 h transceiver, auxiliary interface name 7 6 5 4 3 2 1 0 addr r/wres psb 2154 isdn module data sheet 223 2001-01-24 bchb_ tsdp_ bc1 dps 0 0 tss 4a h r/w 81 h bchb_ tsdp_ bc2 dps 0 0 tss 4b h r/w 85 h tr_ tsdp_ bc1 dps 0 0 tss 4c h r/w tr_ tsdp_ bc2 dps 0 0 tss 4d h r/w cda1_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4e h r/w 00 h cda2_ cr 00en_ tbm en_i1 en_i0 en_o1en_o0 swap 4f h r/w 00 h iom handler (control registers, synchronous transfer interrupt control), monitor handler name 76543210addrr/wres tr_cr (ci_cs=0) en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 50 h r/w tr_cr (ci_cs=1) 00000 cs2-0 50 h r/w bcha_ cr dps_ d 0 en_d en_ bc2 en_ bc1 cs2-0 51 h r/w 80 h bchb_ cr dps_ d 0 en_d en_ bc2 en_ bc1 cs2-0 52 h r/w 81 h dci_cr (ci_cs=0) dps_ ci1 en_ ci1 d_ en_d d_ en_b2 d_ en_b1 cs2-0 53 h r/w psb 2154 isdn module data sheet 224 2001-01-24 dcic_cr (ci_cs=1) 00000 cs2-0 53 h r/w mon_cr dps en_ mon 000 cs2-0 54 h r/w sds_cr ens_ tss ens_ tss+1 ens_ tss+3 tss 55 h r/w 00 h reserved 56 h iom_cr spu 0 ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom 57 h r/w 08 h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0 0 0 0 ack 21 ack 20 ack 11 ack 10 58 h w00 h msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h sds_ conf 0000diom_ inv diom_ sds 0sds_ bcl 5a h r/w 00 h mcda mcda21 mcda20 mcda11 mcda10 5b h rff h mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosr mdr mer mda mab 0 0 0 0 5d h r00 h mocr mre mrc mie mxc 0 0 0 0 5e h r/w 00 h msta 00000mac0tout5f h r00 h mconf0000000tout5f h w00 h psb 2154 isdn module data sheet 225 2001-01-24 interrupt, general configuration registers name 7 6 5 4 3 2 1 0 addr r/wres ista ica icb st cic aux tran mos icd 60 h r00 h ista_ini t 60 h wff h auxi 0 0 eaw wov tin3 tin2 int2 int1 61 h r00 h auxm 1 1 eaw wov tin3 tin2 int2 int1 61 h wff h mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 62 h r/w 00 h reserved 63 h r/w 00 h id 0 0 design 64 h r01 h sres res_ ci res_ bcha res_ bchb res_ mon res_ dch res_ iom res_ tr res_ rsto 64 h w00 h timr3 tmd 0 cnt 65 h r/w 00 h reserved 66 h - 6f h psb 2154 isdn module data sheet 226 2001-01-24 b-channel hdlc control registers (channel a / b) name 76543210addrr/wres istab rme rpf rfo xpr 0 xdu 0 0 70 h /80 h r10 h maskb rme rpf rfo xpr 1 xdu 1 1 70 h /80 h wff h starb xdov xfw 0 0 raci 0 xaci 0 71 h /81 h r40 h cmdrb rmc rres 0 0 xtf 0 xme xres 71 h /81 h w00 h modeb mds2 mds1 mds0 0 rac 0 0 0 72 h /82 h r/w c0 h exmb xfbs rfbs sra xcrc rcrc 0 itf 73 h /83 h r/w 00 h reserved 74 h /84 h rah1 rah1 0 mha 75 h /85 h w00 h rah2 rah2 0 mla 76 h /86 h w00 h rbclb rbc7 rbc0 76 h /86 h r00 h rbchb 0 0 0 ov rbc11 rbc8 77 h /87 h r00 h ral1 ral1 77 h /87 h w00 h ral2 ral2 78 h /88 h w00 h rstab vfr rdo crc rab ha1 ha0 c/r la 78 h /88 h r0e h tmb 0000000tlp79 h /89 h r/w 00 h rfifob b-channel receive fifo 7a h / 8a h r xfifob b-channel transmit fifo 7a h / 8a h w reserved 7b h - 7f h 8b h - 8f h psb 2154 isdn module data sheet 227 2001-01-24 5.8.1 d-channel hdlc control and c/i registers 5.8.1.1 rfifod - receive fifo d-channel a read access to any address within the range 00h-1fh gives access to the ? current ? fifo location selected by an internal pointer which is automatically incremented after each read access. the rfifod contains up to 32 bytes of received data. after an istad.rpf interrupt, a complete data block is available. the block size can be 4, 8, 16 or 32 bytes depending on the exmd2.rfbs setting. after an istad.rme interrupt, the number of received bytes can be obtained by reading the rbcld register. 5.8.1.2 xfifod - transmit fifo d-channel a write access to any address within the range 00-1f h gives access to the ? current ? fifo location selected by an internal pointer which is automatically incremented after each write access. depending on exmd2.xfbs up to 16 or 32 bytes of transmit data can be written to the xfifod following an istad.xpr interrupt. 70 rfifod receive data rd (00-1f) 70 xfifod transmit data wr (00-1f) psb 2154 isdn module data sheet 228 2001-01-24 5.8.1.3 istad - interrupt status register d-channel value after reset: 10 h rme ... receive message end one complete frame of length less than or equal to the defined block size (exmd1.rfbs) or the last part of a frame of length greater than the defined block size has been received. the contents are available in the rfifod. the message length and additional information may be obtained from rbchd and rbcld and the rstad register. rpf ... receive pool full a data block of a frame longer than the defined block size (exmd1.rfbs) has been received and is available in the rfifod. the frame is not yet complete. rfo ... receive frame overflow the received data of a frame could not be stored, because the rfifod is occupied. the whole message is lost. this interrupt can be used for statistical purposes and indicates that the microcontroller does not respond quickly enough to an rpf or rme interrupt (istad). xpr ... transmit pool ready a data block of up to the defined block size 16 or 32 (exmd1.xfbs) can be written to the xfifod. an xpr interrupt will be generated in the following cases: after an xtf or xme command as soon as the 16 or 32 bytes in the xfifo are available and the frame is not yet complete after an xtf together with an xme command is issued, when the whole frame has been transmitted after a reset of the transmitter (xres) after a device reset 70 istad rme rpf rfo xpr xmr xdu 0 0 rd (20) psb 2154 isdn module data sheet 229 2001-01-24 xmr ... transmit message repeat the transmission of the last frame has to be repeated because a collision on the s bus has been detected after the 16 th /32 nd data byte of a transmit frame. if an xmr interrupt occurs the transmit fifo is locked until the xmr interrupt is read by the host (interrupt cannot be read if masked in maskd). xdu ... transmit data underrun the current transmission of a frame is aborted by transmitting seven ? 1 ? s because the xfifod holds no further data. this interrupt occurs whenever the microcontroller has failed to respond to an xpr interrupt (istad register) quickly enough, after having initiated a transmission and the message to be transmitted is not yet complete. if an xdu interrupt occurs the transmit fifo is locked until the xdu interrupt is read by the host (interrupt cannot be read if masked in maskd). 5.8.1.4 maskd - mask register d-channel value after reset: ff h each interrupt source in the istad register can selectively be masked by setting the corresponding bit in maskd to ? 1 ? . masked interrupt status bits are not indicated when istad is read. instead, they remain internally stored and pending until the mask bit is reset to ? 0 ? . 70 maskd rme rpf rfo xpr xmr xdu 1 1 wr (20) psb 2154 isdn module data sheet 230 2001-01-24 5.8.1.5 stard - status register d-channel value after reset: 40 h xdov ... transmit data overflow more than 16 or 32 bytes (according to selected block size) have been written to the xfifod, i.e. data has been overwritten. xfw ... transmit fifo write enable data can be written to the xfifod. this bit may be polled instead of (or in addition to) using the xpr interrupt. raci ... receiver active indication the d-channel hdlc receiver is active when raci = ? 1 ? . this bit may be polled. the raci bit is set active after a begin flag has been received and is reset after receiving an abort sequence. xaci ... transmitter active indication the d-channel hdlc-transmitter is active when xaci = ? 1 ? . this bit may be polled. the xaci-bit is active when an xtf-command is issued and the frame has not been completely transmitted 70 stard xdov xfw 0 0 raci 0 xaci 0 rd (21) psb 2154 isdn module data sheet 231 2001-01-24 5.8.1.6 cmdrd - command register d-channel value after reset: 00 h rmc ... receive message complete reaction to rpf (receive pool full) or rme (receive message end) interrupt. by setting this bit, the microcontroller confirms that it has fetched the data, and indicates that the corresponding space in the rfifod may be released. rres ... receiver reset hdlc receiver is reset, the rfifod is cleared of any data. sti ... start timer 2 the siuc-x timer 2 is started when sti is set to one. the timer is stopped by writing to the timr2 register. note: timer 3 is controlled by the timr3 register only. xtf ... transmit transparent frame after having written up to 16 or 32 bytes (exmd1.xfbs) to the xfifod, the microcontroller initiates the transmission of a transparent frame by setting this bit to ? 1 ? . the opening flag is automatically added to the message by the siuc-x (except in the extended transparent mode where no flags are used). xme ... transmit message end by setting this bit to ? 1 ? the microcontroller indicates that the data block written last to the xfifod completes the corresponding frame. the siuc-x terminates the transmission by appending the crc (if exmd1.xcrc=0) and the closing flag sequence to the data (except in the extended transparent mode where no such framing is used). xres ... transmitter reset the d-channel hdlc transmitter is reset and the xfifod is cleared of any data. this command can be used by the microcontroller to abort a frame currently in transmission. note: after an xpr interrupt further data has to be written to the xfifod and the appropriate transmit command (xtf) has to be written to the cmdrd register again to continue transmission, when the current frame is not yet complete (see 70 cmdrd rmc rres 0 sti xtf 0 xme xres wr (21) psb 2154 isdn module data sheet 232 2001-01-24 also xpr in istad). during frame transmission, the 0-bit insertion according to the hdlc bit-stuffing mechanism is done automatically. 5.8.1.7 moded - mode register value after reset: c0 h mds2-0 ... mode select determines the message transfer mode of the hdlc controller, as follows: 70 moded mds2 mds1 mds0 0 rac dim2 dim1 dim0 rd/wr (22) mds2-0 mode number of address bytes address comparison remark 1.byte 2.byte 0 0 0reserved 0 0 1reserved 0 1 0non-auto mode 1tei1,tei2 ? one-byte address compare. 0 1 1non-auto mode 2 sap1,sap2,sapgtei1,tei2,teigtwo-byte address compare. 1 0 0extended transparent mode 1 1 0transparent mode 0 ?? ? no address compare. all frames accepted. 1 1 1transparent mode 1 > 1 sap1,sap2,sapg ? high-byte address compare. 1 0 1transparent mode 2 > 1 ? tei1,tei2,teiglow-byte address compare. psb 2154 isdn module data sheet 233 2001-01-24 note: sap1, sap2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); sapg = fixed value fc / fe h . tei1, tei2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; teig = fixed value ff h two different methods of the high byte and/or low byte address comparison can be selected by setting sap1.mha and/or sap2.mla. rac ... receiver active the d-channel hdlc receiver is activated when this bit is set to ? 1 ? . if set to ? 0 ? the hdlc data is not evaluated in the receiver. dim2-0 ... digital interface modes these bits define the characteristics of the iom data ports (du, dd). the dim0 bit enables/disables the collission detection. the dim1 bit enables/disables the tic bus access. the effect of the individual dim bits is summarized in the table below . dim2 dim1 dim0 characteristics 0 0 transparent d-channel, the collission detection is disabled 0 1 stop/go bit evaluated for d-channel access handling 0 0 last octet of iom channel 2 used for tic bus access 0 1 tic bus access is disabled 1 x x reserved psb 2154 isdn module data sheet 234 2001-01-24 5.8.1.8 exmd1- extended mode register d-channel 1 value after reset: 00 h xfbs ? transmit fifo block size 0 ? block size for the transmit fifo data is 32 byte 1 ? block size for the transmit fifo data is 16 byte note: a change of xfbs will take effect after a receiver command (cmdrd.xme, cmdrd.xres, cmdrd.xtf) has been written. rfbs ? receive fifo block size note: a change of rfbs will take effect after a transmitter command (cmdr.rmc, cmdr.rres,) has been written sra ? store receive address 0 ? receive address isn ? t stored in the rfifod 1 ? receive address is stored in the rfifod xcrc ? transmit crc 0 ? crc is transmitted 1 ? crc isn ? t transmitted rcrc ? receive crc 0 ? crc isn ? t stored in the rfifod 1 ? crc is stored in the rfifod 70 exmd1 xfbs rfbs sra xcrc rcrc 0 itf rd/wr (23) rfbs block size receive fifo bit 6 bit5 0 0 32 byte 0 1 16 byte 108 byte 114 byte psb 2154 isdn module data sheet 235 2001-01-24 itf ? interframe time fill selects the inter-frame time fill signal which is transmitted between hdlc-frames. 0 ? idle (continuous ? 1 ? ) 1 ? flags (sequence of patterns: ? 0111 1110 ? ) note: itf must be set to ? 0 ? for power down mode. in applications with d-channel access handling (collision resolution), the only possible inter-frame time fill is idle (continuous ? 1 ? ) . otherwise the d-channel on the s/t-bus cannot be accessed 5.8.1.9 timr2 - timer 2 register value after reset: 00 h cnt ... timer counter cnt together with value determines the time period t after which a auxi.tin2 interrupt will be generated: cnt=0...6: t = cnt x 2.048 sec + t1 with t1 = ( value+1 ) x 0.064 sec cnt=7: t = t1 = ( value+1 ) x 0.064 sec (generated periodically) the timer can be started by setting the sti-bit in cmdrd and will be stopped when a tin2 interrupt is generated or the timr2 register is written. note: if cnt is set to 7, a tin interrupt is indefinitely generated after every expiration of t1 (i.e. t = t1). value ... timer value determines the value of the timer value t1 = ( value + 1 ) x 0.064 sec . 754 0 timr2 cnt value rd/wr (24) psb 2154 isdn module data sheet 236 2001-01-24 5.8.1.10 sap1 - sapi1 register value after reset: fc h sapi1 ... sapi1 value value of the first programmable service access point identifier (sapi) according to the isdn lapd protocol. mha... mask high address 0 ? the sapi address of an incomming frame is compared with sap1, sap2, sapg. 1 ? the sapi address of an incomming frame is compared with sap1 and sapg. sap1 can be masked with sap2 thereby bit positions of sap1 are not compared if they are set to ? 1 ? in sap2. 5.8.1.11 sap2 - sapi2 register value after reset: fc h sapi2 ... sapi2 value value of the second programmable service access point identifier (sapi) according to the isdn lapd-protocol. mla... mask low address 0 ? the tei address of an incomming frame is compared with tei1, tei2 and teig. 1 ? the tei address of an incomming frame is compared with tei1 and teig. tei1 can be masked with tei2 thereby bit positions of tei1 are not compared if they are set to ? 1 ? in tei2. 70 sap1 sapi1 0 mha wr (25) 70 sap2 sapi2 0 mla wr (26) psb 2154 isdn module data sheet 237 2001-01-24 5.8.1.12 rbcld - receive frame byte count low d-channel value after reset: 00 h rbc7-0 ... receive byte count eight least significant bits of the total number of bytes in a received message (see rbchd register). 5.8.1.13 rbchd - receive frame byte count high d-channel value after reset: 00 h . ov ... overflow a ? 1 ? in this bit position indicates a message longer than (2 12 - 1) = 4095 bytes . rbc8-11 ... receive byte count four most significant bits of the total number of bytes in a received message (see rbcld register). note: normally rbchd and rbcld should be read by the microcontroller after an rme-interrupt in order to determine the number of bytes to be read from the rfifod, and the total message length. the contents of the registers are valid only after an rme or rpf interrupt, and remain so until the frame is acknowledged via the rmc bit or rres. 70 rbcld rbc7 rbc0 rd (26) 70 rbchd 0 0 0 ov rbc11 rbc8 rd (27) psb 2154 isdn module data sheet 238 2001-01-24 5.8.1.14 tei1 - tei1 register 1 value after reset: ff h tei1 ... terminal endpoint identifier in all message transfer modes except in transparent modes 0, 1 and extended transparent mode, tei1 is used by the siuc-x for address recognition. in the case of a two-byte address field, it contains the value of the first programmable terminal endpoint identifier according to the isdn lapd-protocol. in non-automodes with one-byte address field, tei1 is a command address, according to x.25 lapb. ea1 ... address field extension bit this bit is set to ? 1 ? according to hdlc/lapd. 5.8.1.15 tei2 - tei2 register value after reset: ff h tei2 ... terminal endpoint identifier in all message transfer modes except in transparent modes 0, 1 and extended transparent mode, tei2 is used by the siuc-x for address recognition. in the case of a two-byte address field, it contains the value of the second programmable terminal endpoint identifier according of the isdn lapd-protocol. in non-auto-modes with one-byte address field, tei2 is a response address, according to x.25 lapd. ea2 ... address field extension bit this bit is to be set to ? 1 ? according to hdlc/lapd. 70 tei1 tei1 ea1 wr (27) 70 tei2 tei2 ea2 wr (28) psb 2154 isdn module data sheet 239 2001-01-24 5.8.1.16 rstad - receive status register d-channel value after reset: 0f h for general information please refer to chapter 5.6 . vfr... valid frame determines whether a valid frame has been received. the frame is valid (1) or invalid (0). a frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). rdo ... receive data overflow if rdo=1, at least one byte of the frame has been lost, because it could not be stored in rfifod. as opposed to the istad.rfo an rdo indicates that the beginning of a frame has been received but not all bytes could be stored as the rfifod was temporarily full. crc ... crc check the crc is correct (1) or incorrect (0). rab ... receive message aborted the receive message was aborted by the remote station (1), i.e. a sequence of seven 1 ? s was detected before a closing flag. sa1-0 ... sapi address identification ta ... tei address identification sa1-0 are significant in non-automode with a two-byte address field, as well as in transparent mode 3. ta is significant in all modes except in transparent modes 0 and 1. two programmable sapi values (sap1, sap2) plus a fixed group sapi (sapg of value fc h /fe h ), and two programmable tei values (tei1, tei2) plus a fixed group tei (teig of value ff h ), are available for address comparison. the result of the address comparison is given by sa1-0 and ta, as follows: c/r ... command/response the c/r bit contains the c/r bit of the received frame (bit1 in the sapi address). 70 rstad vfr rdo crc rab sa1 sa0 c/r ta rd (28) psb 2154 isdn module data sheet 240 2001-01-24 note: the contents of rstad corresponds to the last received hdlc frame; it is duplicated into rfifod for every frame (last byte of frame) note: if sap1 and sap2 contain identical values, the combination sap1/2-teig will only be indicated by sa1,0= ? 10 ? (i.e. the value ? 00 ? will not occur in this case). 5.8.1.17 tmd -test mode register d-channel value after reset: 00 h for general information please refer to chapter 5.2.11 . tlp ... test loop the tx path of layer-2 is internally connected with the rx path of layer-2. data coming from the layer 1 controller will not be forwarded to the layer 2 controller. the setting of tlp is only valid if the iom interface is active. address match with mds2-0 mode sa1 sa0 ta 1 st byte 2 nd byte 010 non-auto/8 mode x x x x 0 1 tei2 tei1 - - 011 non-auto/16 mode 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 sap2 sap2 sapg sapg sap1 sap1 teig tei2 teig tei1 or tei2 teig tei1 111 transparent mode 1 0 0 1 0 1 0 x x x sap2 sapg sap1 - - - 101 transparent mode 2 - - - - 0 1 - - teig tei1 or tei2 1 1 x reserved 70 tmd 0000000tlprd/wr (29) psb 2154 isdn module data sheet 241 2001-01-24 5.8.1.18 cir0 - command/indication receive 0 value after reset: f3 h codr0 ... c/i code 0 receive value of the received command/indication code. a c/i-code is loaded in codr0 only after being the same in two consecutive iom-frames and the previous code has been read from cir0. cic0 ... c/i code 0 change a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom-frames. it is reset by a read of cir0. cic1 ... c/i code 1 change a change in the received command/indication code in iom-channel 1 has been recognized. this bit is set when a new code is detected in one iom-frame. it is reset by a read of cir0. s/g ... stop/go bit monitoring indicates the availability of the upstream d-channel on the s/t interface. 1: stop 0: go bas ... bus access status indicates the state of the tic-bus: 0: the siuc-x itself occupies the d- and c/i-channel 1: another device occupies the d- and c/i-channel note: the codr0 bits are updated every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive valid new codes are detected and cir0 is not read, only the first and the last c/i code is made available in cir0 at the first and second read of that register, respectively. 70 cir0 codr0 cic0 cic1 s/g bas rd (2e) psb 2154 isdn module data sheet 242 2001-01-24 5.8.1.19 cix0 - command/indication transmit 0 value after reset: fe h codx0 ... c/i-code 0 transmit code to be transmitted in the c/i-channel 0. the code is only transmitted if the tic bus is occupied. if tic bus is enabled but occupied by another device, only ? 1s ? are transmitted. tba2-0 ... tic bus address defines the individual address for the siuc-x on the iom bus. this address is used to access the c/i- and d-channel on the iom interface. note: if only one device is liable to transmit in the c/i- and d-channels of the iom it should always be given the address value ? 7 ? . bac ... bus access control only valid if the tic-bus feature is enabled (moded.dim2-0). if this bit is set, the siuc-x will try to access the tic-bus to occupy the c/i-channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the siuc-x with tic-bus address (tba2- 0, stcr register) ? 7 ? , which has the lowest priority in a bus configuration. 5.8.1.20 cir1 - command/indication receive 1 value after reset: fe h codr1 ... c/i-code 1 receive cicw, ci1e ... c/i-channel width, c/i-channel 1 interrupt enable these two bits contain the read back values from cix1 register (see below). 70 cix0 codx0 tba2 tba1 tba0 bac wr (2e) 70 cir1 codr1 cicw ci1e rd (2f) psb 2154 isdn module data sheet 243 2001-01-24 5.8.1.21 cix1 - command/indication transmit 1 value after reset: fe h codx1 ... c/i-code 1 transmit bits 7-2 of c/i1-channel timeslot. cicw... c/i-channel width cicw selects between a 4 bit ( ? 0 ? ) and 6 bit ( ? 1 ? ) c/i1 channel width. the c/i1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. however in write direction the full codx1 code is transmitted, i.e. the host must write the higher two bits to ? 1 ? . ci1e ... c/i-channel 1 interrupt enable interrupt generation ista.cic of cir0.cic1 is enabled (1) or masked (0). 70 cix1 codx1 cicw ci1e wr (2f) psb 2154 isdn module data sheet 244 2001-01-24 5.8.2 transceiver registers 5.8.2.1 tr_conf0 - transceiver configuration register 0 value after reset: 01 h dis_tr ... disable transceiver all layer-1 functions are disabled by setting dis_tr = 1. the d- and b-channel hdlc controllers can still operate via iom-2 while dcl and fsc pins become input. in order to reenable the transceiver again, a reset to the transceiver must be issued (sres.res_tr = 1). the transceiver must not be reenabled by setting dis_tr from ? 1 ? to ? 0 ? . for general information please refer to chapter 5.2.10 . en_icv ... enable illegal code violation 0: normal operation 1: icv enabled. the receipt of at least one illegal code violation within one multiframe is indicated by the c/i indication ? 1011 ? (cvr) in two consecutive iom frames. l1sw ... enable layer 1 state machine in software 0: layer 1 state machine of the siuc-x is used 1: layer 1 state machine is disabled. the functionality can be realized in software. the commands can be written to register tr_cmd and the status can be read from tr_sta. for general information please refer to chapter 5.3 . exlp ... external loop in case the analog loopback is activated with c/i = arl or with the lp_a bit in the tr_cmd register the loop is a 0: internal loop next to the line pins 1: external loop which has to be closed between sr1/2 and sx1/sx2 note: the external loop is only useful if bit dis_tx of register tr_conf2 is set to ? 0 ? . for general information please refer to chapter 5.2.11 . 70 tr_ conf0 dis_ tr 0en_ icv 0 l1sw 0 exlp ldd rd/wr (30) psb 2154 isdn module data sheet 245 2001-01-24 ldd ... level detection discard 0: automatic clock generation after detection of any signal on the line in power down state 1: no clock generation after detection of any signal on the line in power down state note:if an interrupt by the level detect circuitry is generated, the microcontroller has to set this bit to ? 0 ? for an activation of the s/t interface. for general information please refer to chapter 5.2.9 and chapter 5.5.7 . 5.8.2.2 tr_conf1 - transceiver configuration register 1 value after reset: 0x h rpll_adj ... receive pll adjustment 0: dpll tracking step is 0.5 xtal period per s-frame 1: dpll tracking step is 1 xtal period per s-frame en_sfsc ... enable short fsc 0: no short fsc is generated 1: a short fsc is generated once per multiframe (every 40th iom frame) x ... undefined the value of these bits depends on the selected mode. it is important to note that these bits must not be overwritten to a different value when accessing this register. 70 tr_ conf1 0rpll_ adj en_ sfsc 0 0 x x x rd/wr (31) psb 2154 isdn module data sheet 246 2001-01-24 5.8.2.3 tr_conf2 - transmitter configuration register 2 value after reset: 80 h dis_tx ... disable line driver 0: transmitter is enabled 1: transmitter is disabled for general information please refer to chapter 5.2.10 . pds ... phase deviation select defines the phase deviation of the s-transmitter. 0: the phase deviation is 2 s-bits minus 7 oscillator periods plus analog delay plus delay of the external circuitry. 1: the phase deviation is 2 s-bits minus 9 oscillator periods plus analog delay plus delay of the external circuitry. for general information please refer to chapter 5.2.8 . rlp ... remote loop 0: remote loop open 1: remote loop closed this test mode can also be programmed in tr_cmd.lp_a. for general information please refer to chapter 5.2.11 . sgp ... stop/go bit polarity defines the polarity of the s/g bit output on pin sgo (multiplexed function of aux7). 0: low active (sgo=0 means ? go ? ; sgo=1 means ? stop ? ) 1: high active (sgo=1 means ? go ? ; sgo=0 means ? stop ? ) sgd ... stop/go bit duration defines the duration of the s/g bit output on pin sgo (multiplexed function of aux7). 0: active during the d-channel timeslot 1: active during the whole corresponding iom frame (starts and ends with the beginning of the d-channel timeslot) 70 tr_ conf2 dis_ tx pds 0 rlp 0 0 sgp sgd rd/wr (32) psb 2154 isdn module data sheet 247 2001-01-24 note:outside the active window of sgo (defined in sgd) the level on pin sgo remains in the ? stop ? -state depending on the selected polarity (sgp), i.e. sgo=1 (if sgp=0) or sgo=0 (if sgp=1) outside the active window. 5.8.2.4 tr_sta - transceiver status register value after reset: 00 h important: this register is used only if the layer 1 state machine of the siuc-x is disabled (tr_conf0.l1sw = 1) and implemented in software! with the siuc-x layer 1 state machine enabled, the signals from this register are automatically evaluated. for general information please refer to chapter 5.3 . rinf ... receiver info 00: received info 0 01: received any signal except info 1 - 4 10: received info 2 11: received info 4 icv ... illegal code violation 0: no illegal code violation is detected 1: illegal code violation (ansi t1.605) in data stream is detected fsyn ... frame synchronization state 0: the s/t receiver is not synchronized 1: the s/t receiver has synchronized to the framing bit f ld ... level detection 0: no receive signal has been detected on the line. 1: any receive signal has been detected on the line. 70 tr_ sta rinf 0 icv 0 fsyn 0 ld rd (33) psb 2154 isdn module data sheet 248 2001-01-24 5.8.2.5 tr_cmd - transceiver command register value after reset: 08 h important: this register is used only if the layer 1 state machine of the siuc-x is disabled (tr_conf0.l1sw = 1) and implemented in software! with the siuc-x layer 1 state machine enabled, the signals from this register are automatically generated. xinf ... transmit info 000: transmit info 0 001: reserved 010: transmit info 1 011: transmit info 3 100: send continous pulses at 192 kbit/s alternating or 96 khz rectangular, respectively (scp) 101: send single pulses at 4 kbit/s with alternating polarity corresponding to 2 khz fundamental mode (ssp) 11x: reserved dprio ... d-channel priority 0: priority class 1 for d channel access on s interface 1: priority class 2 for d channel access on s interface tddis ... transmit data disabled (te mode) 0: the b and d channel data are transparently transmitted on the s/t interface if info 3 is being transmitted 1: the b and d channel data are set to logical ? 1 ? on the s/t interface if info 3 is being transmitted pd ... power down 0: the transceiver is set to operational mode 1: the transceiver is set to power down mode 70 tr_ cmd xinf dprio tddis pd lp_a 0 rd/wr (34) psb 2154 isdn module data sheet 249 2001-01-24 note: this bit should not be used with active layer 1 state machine of the siuc-x to power down the device. instead, the c/i commands should be used. for general information please refer to chapter 5.3.1.2 . lp_a ... loop analog the setting of this bit corresponds to the c/i command arl. 0:analog loop is open 1:analog loop is closed internally or externally according to the exlp bit in the tr_conf0 register for general information please refer to chapter 5.2.11 . 5.8.2.6 sqrr1 - s/q-channel receive register 1 value after reset: 40 h for general information please refer to chapter 5.2.2 . msyn ... multiframe synchronization state 0: the s/t receiver has not synchronized to the received f a and m bits 1: the s/t receiver has synchronized to the received f a and m bits mfen ... multiframe enable read-back of the mfen bit of the sqxr register sqr11-14 ... received s bits received s bits in frames 1, 6, 11 and 16 (te mode). 70 sqrr msyn mfen 0 0 sqr11 sqr12 sqr13 sqr14 rd (35) psb 2154 isdn module data sheet 250 2001-01-24 5.8.2.7 sqxr1- s/q-channel tx register 1 value after reset: 4f h mfen ... multiframe enable used to enable or disable the multiframe structure (see chapter 5.2.2 ) 0: s/t multiframe is disabled 1: s/t multiframe is enabled readback value in sqrr1. sqx11-14 ... transmitted s/q bits transmitted q bits (f a bit position) in frames 1, 6, 11 and 16 (te mode). 5.8.2.8 sqrr2 - s/q-channel receive register 2 value after reset: 00 h sqr21-24, sqr31-34... received s bits (te mode only) received s bits in frames 2, 7, 12 and 17 (sqr21-24, subchannel 2), and in frames 3, 8, 13 and 18 (sqr31-34, subchannel 3). 70 sqxr1 0 mfen 0 0 sqx11 sqx12 sqx13 sqx14 wr (35) 70 sqrr2 sqr21 sqr22 sqr23 sqr24 sqr31 sqr32 sqr33 sqr34 rd (36) psb 2154 isdn module data sheet 251 2001-01-24 5.8.2.9 sqrr3 - s/q-channel receive register 3 value after reset: 00 h sqr41-44, sqr51-54... received s bits (te mode only) received s bits in frames 4, 9, 14 and 19 (sqr41-44, subchannel 4), and in frames 5, 10, 15 and 20 (sqr51-54, subchannel 5). 5.8.2.10 istatr - interrupt status register transceiver value after reset: 00 h for all interrupts in the istatr register the following logical states are defined: 0: interrupt is not acitvated 1: interrupt is acitvated x ... reserved bits set to ? 1 ? in this bit position must be ignored. ld ... level detection any receive signal has been detected on the line. this bit is set to ? 1 ? (i.e. an interrupt is generated if not masked) as long as any receiver signal is detected on the line. ric ... receiver info change ric is activated if one of the tr_sta bits rinf or icv has changed. this bit is reset by reading this register. 70 sqrr3 sqr41 sqr42 sqr43 sqr44 sqr51 sqr52 sqr53 sqr54 rd (37) 70 istatr x x x x ld ric sqc sqw rd (38) psb 2154 isdn module data sheet 252 2001-01-24 sqc ... s/q-channel change a change in the received s-channel has been detected. the new code can be read from the sqrxx bits of registers sqrr1-3 within the next multiframe. this bit is reset by a read access to the corresponding sqrrx register. sqw ... s/q-channel writable the s/q channel data for the next multiframe is writable. the register for the q (s) bits to be transmitted (received) has to be written (read) within the next multiframe. this bit is reset by writing register sqxrx. this timing signal is indicated with the start of every multiframe. data which is written right after sqw-indication will be transmitted with the start of the following multiframe. data which is written before sqw-indication is transmitted in the multiframe which is indicated by sqw. sqw and sqc could be generated at the same time. 5.8.2.11 masktr - mask transceiver interrupt value after reset: ff h the transceiver interrupts ld, ric, sqc and sqw are enabled (0) or disabled (1). 70 masktr 1 1 1 1 ld ric sqc sqw rd/wr (39) psb 2154 isdn module data sheet 253 2001-01-24 5.8.2.12 tr_mode - transceiver mode register 1 value after reset: 00 h d_slice ... d-channel slice determines the 2-bit position of the d-channel within the selected octett. 00: bit 7 and 6 (default position on iom-2 interface) 01: bit 5 and 4 10: bit 3 and 2 11: bit 1 and 0 note: shifting the d-channel to a different position may be usefull for special test purposes. mode2-0 ... transceiver mode 000: te mode 000 : all other codes reserved 70 tr_ mode d_slice 0 0 0 mode 2 mode 1 mode 0 rd/wr (3a) psb 2154 isdn module data sheet 254 2001-01-24 5.8.3 auxiliary interface registers 5.8.3.1 acfg1 - auxiliary configuration register 1 value after reset: 00 h for general information please refer to chapter 8.3.1 . od7-0 ... output driver select for aux7 - aux0 0: output is open drain 1: output is push/pull note: the odx configuration is only valid if the corresponding output is enabled in the aoe register. aux7 and aux6 provide internal pull up resistors which are only available as inputs and in output/open drain mode, but disabled in output / push/pull mode. 5.8.3.2 acfg2 - auxiliary configuration register 2 value after reset: 00 h a7sel ... aux7 function select 0: pin aux7 provides normal i/o functionality. 1: pin aux7 provides the s/g bit output (sgo) from the iom dd-line. bit aoe.oe7 is don ? t care, the output characteristic (push pull or open drain) can be selected via acfg1.od7. a5sel ... aux5 function select 0: pin aux5 provides normal i/o functionality. 1: pin aux5 provides an fsc or bcl signal output (fbout) which is selected in acfg2.fbs. bit aoe.oe5 is don ? t care, the output characteristic (push pull or open drain) can be selected via acfg1.od5. 70 acfg1 od7 od6 od5 od4 od3 od2 od1 od0 rd/wr (3c) 70 acfg2 a7sel a5sel fbs a4sel acl led el2 el1 rd/wr (3d) psb 2154 isdn module data sheet 255 2001-01-24 for general information please refer to chapter 8.1 . fbs ... fsc/bcl output select 0: fsc is output on pin aux5. 1: bcl (single bit clock) is output on pin aux5. note: this selection has only effect on pin aux5 if fbout is enabled (a5sel=1). for general information please refer to chapter 8.1 . a4sel ... aux4 function select 0: pin aux4 provides normal i/o functionality. 1: pin aux4 supports multiframe synchronization and is used as m-bit output in te mode. bit aoe.oe4 is don ? t care, the output characteristic (push pull or open drain) can be selected via acfg1.od4. for general information please refer to chapter 5.2.3 . acl ... acl function select 0: pin acl automatically indicates the s-bus activation status by a low level. 1: the output state of acl is programmable by the host in bit led. note: an led with preresistance may directly be connected to acl. led ... led control if enabled (acl=1) the led with preresistance connected between vdd and acl is switched ... 0: off (high level on pin acl) 1: on (low level on pin acl) el1, 2 ... edge/level triggered interrupt input for int1 , int2 0: a negative level ... 1: a negative edge ... on int1/2 (pins aux6/7) generates an interrupt to the siuc-x. note: an interrupt is only generated if the corresponding mask bit in auxm is reset. this configuration is only valid if the corresponding output enable bit in aoe is disabled. for general information please refer to chapter 8.3.1 . psb 2154 isdn module data sheet 256 2001-01-24 5.8.3.3 aoe - auxiliary output enable register value after reset: ff h for general information please refer to chapter 8.3.1 . oe7-0 ... output enable for aux7 - aux0 0: pin aux7-0 is configured as output. the value of the corresponding bit in the atx register is driven on aux7-0. 1: pin aux7-0 is configured as input. the value of the corresponding bit can be read from the arx register. note: if pins aux7, aux6 are to be used as interrupt input, oe7, oe6 must be set to 1. if pins aux7, aux5 and aux4 are not used as i/o pins (see acfg2), the corresponding oex bit cannot be set, but delivers the mode dependent direction (input/output) in that function upon a read access. if the secondary function is disabled, the direction of the pin as i/o pin is valid again. 5.8.3.4 arx - auxiliary interface receive register value after reset: (not defined) ar7-0 ... auxiliary receive the value of ar7-0 always reflects the level at pin aux7-0 at the time when arx is read by the host even if a pin is configured as output. if the mask bit for aux7, 6 is set in the maska register, no interrupt is generated to the siuc-x, however, the current state at pin aux7,6 can be read from ar7,6 70 aoe oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 rd/wr (3e) 70 arx ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 rd (3f) psb 2154 isdn module data sheet 257 2001-01-24 5.8.3.5 atx - auxiliary interface transmit register value after reset: 00 h at7-0 ... auxiliary transmit a ? 0 ? or ? 1 ? in at7-0 will drive a low or a high level at pin aux7-0 if the corresponding output is enabled in the aoe register. 5.8.4 iom-2 and monitor handler 5.8.4.1 cdaxy - controller data access register xy data registers cdaxy which can be accessed from the controller. 70 atx at7 at6 at5 at4 at3 at2 at1 at0 wr (3f) 70 cdaxy controller data access register rd/wr (40-43) register register address value after reset cda10 40 h ff h cda11 41 h ff h cda20 42 h ff h cda21 43 h ff h psb 2154 isdn module data sheet 258 2001-01-24 5.8.4.2 xxx_tsdpxy - time slot and data port selection for chxy this register determines the time slots and the data ports on the iom-2 interface for the data channels ? xy ? of the functional units ? xxx ? which are controller data access (cda), b-channel controllers (bcha, bchb) and transceiver (tr). each of the two b-channel controllers (bcha, bchb) can access any combination of two 8-bit timeslots and one 2-bit timeslot (e.g. 16-bit access to b1+b2 or 18-bit idsl in 2b+d). the position of the two 8-bit timeslots is programmed in bchx_tsdp_bc1 and bchx_tsdp_bc2. the position of the 2-bit timeslot is programmed in bcha_cr and bchb_cr. in the same registers each of the three timeslots is enabled/disabled. the position of b-channel data from the s-interface is programmed in tr_tsdp_bc1 and tr_tsdp_bc2. 70 xxx_ tsdpxy dps 0 0 tss rd/wr (44-4d) register register address value after reset cda_tsdp10 44 h 00 h ( = output on b1-dd) cda_tsdp11 45 h 01 h ( = output on b2-dd) cda_tsdp20 46 h 80 h ( = output on b1-du) cda_tsdp21 47 h 81 h ( = output on b2-du) bcha_tsdp_bc1 48 h 80 h ( = output on b1-du) bcha_tsdp_bc2 49 h 81 h ( = output on b2-du) bchb_tsdp_bc1 4a h 81 h ( = output on b2-du) bchb_tsdp_bc2 4b h 85 h ( = output on ic2-du) tr_tsdp_bc1 4c h 00 h ( = transceiver output on b1-dd), see note tr_tsdp_bc2 4d h 01 h ( = transceiver output on b2-dd), see note psb 2154 isdn module data sheet 259 2001-01-24 dps ... data port selection 0: the data channel xy of the functional unit xxx is output on dd. the data channel xy of the functional unit xxx is input from du. 1: the data channel xy of the functional unit xxx is output on du. the data channel xy of the functional unit xxx is input from dd. note: for the cda (controller data access) data the input is determined by the cda_crx.swap bit. if swap = ? 0 ? the input for the cdaxy data is vice versa to the output setting for cdaxy. if the swap = ? 1 ? the input from cdax0 is vice versa to the output setting of cdax1 and the input from cdax1 is vice versa to the output setting of cdax0. see controller data access description in chapter 5.5.1.1 tss ... timeslot selection selects one of 32 timeslots (0...31) on the iom-2 interface for the data channels. note: the tss reset values for tr_tsdp_bc1/2 are determined by the channel select pins ch2-0 which are mapped to the corresponding bits tss4-2. psb 2154 isdn module data sheet 260 2001-01-24 5.8.4.3 cdax_cr - control register controller data access ch1x for general information please refer to chapter 5.5.1.1 . en_tbm ... enable tic bus monitoring 0: the tic bus monitoring is disabled 1: the tic bus monitoring with the cdax0 register is enabled. the tsdpx0 register must be set to 08 h for monitoring from du or 88 h for monitoring from dd, respectively. en_i1, en_i0 ... enable input cdax0, cdax1 0: the input of the cdax0, cdax1 register is disabled 1: the input of the cdax0, cdax1 register is enabled en_o1, en_o0 ... enable output cdax0, cdax1 0: the output of the cdax0, cdax1 register is disabled 1: the output of the cdax0, cdax1 register is enabled swap ... swap inputs 0: the time slot and data port for the input of the cdaxy register is defined by its own tsdpxy register. the data port for the cdaxy input is vice versa to the output setting for cdaxy. 1: the input (time slot and data port) of the cdax0 is defined by the tsdp register of cdax1 and the input of cdax1 is defined by the tsdp register of cdax0. the data port for the cdax0 input is vice versa to the output setting for cdax1. the data port for the cdax1 input is vice versa to the output setting for cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 to cdax0. the outputs are not affected by the swap bit. 70 cdax_ cr 00en_ tbm en_i1 en_i0 en_o1 en_o0 swap rd/wr (4e-4f) register register address value after reset cda1_cr 4e h 00 h cda2_cr 4f h 00 h psb 2154 isdn module data sheet 261 2001-01-24 5.8.4.4 tr_cr - control register transceiver data (iom_cr.ci_cs=0) value after reset: f8 h read and write access to this register is only possible if iom_cr.ci_cs=0. en_d ... enable d-channel data en_b2r ... enable b2 receive data (transceiver receives from iom) en_b1r ... enable b1 receive data (transceiver receives from iom) en_b2x ... enable b2 transmit data (transceiver transmits to iom) en_b1x ... enable b1 transmit data (transceiver transmits to iom) this register is used to individually enable/disable the d-channel (both, rx and tx direction) and the receive/transmit paths for the b-channels for the s-transceiver. 0: the corresponding data path to the transceiver is disabled. 1: the corresponding data path to the transceiver is enabled. cs2-0 ... channel select for transceiver d-channel this register is used to select one of eight iom channels to which the transceiver d and c/i channel data are related to (also see register trc_cr below). note: the reset value is determined by the channel select pins ch2-0 which are directly mapped to cs2-0. it should be noted that writing tr_cr.cs2-0 will also write to trc_cr.cs2-0 and therefore modify the channel selection for the transceiver c/i data. 70 tr_cr en_ d en_ b2r en_ b1r en_ b2x en_ b1x cs2-0 rd/wr (50) psb 2154 isdn module data sheet 262 2001-01-24 5.8.4.5 trc_cr - control register transceiver c/i (iom_cr.ci_cs=1) value after reset: 00 h write access to this register is possible if iom_cr.ci_cs = 0 or iom_cr.ci_cs = 1. read access to this register is possible only if iom_cr.ci_cs = 1. cs2-0 ... channel select for the transceiver c/i channel this register is used to select one of eight iom channels to which the transceiver c/i channel are related to. the reset value is determined by the channel select pins ch2-0 which are mapped to cs2-0. 70 trc_cr 0 0 0 0 0 cs2-0 rd/wr (50) psb 2154 isdn module data sheet 263 2001-01-24 5.8.4.6 bchx_cr - control register b-channel data the registers bcha_tsdp_bc1/2 and bchb_tsdp_bc1/2 (see above) select the iom-2 timeslots for b-channel access. for each of the b-channel controllers (bcha, bchb) two 8-bit timeslots can be selected (position and direction). this register bchx_cr is used to select the position and direction of the 2-bit timeslot for each of the two b-channel controllers and each of the three selected timeslots (2 x 8- bit and 2-bit) is individually enabled/disabled. dps ... data port selection for d-channel timeslot access 0: the b-channel controller data is output on dd. the b-channel controller data is input from du. 1: the b-channel controller data is output on du. the b-channel controller data is input from dd. en_d ... enable d-channel timeslot (2-bit) for b-channel controller access en_bc2 ... enable b2-channel timeslot (8-bit) for b-channel controller access en_bc1 ... enable b1-channel timeslot (8-bit) for b-channel controller access these bits individually enable/disable the b-channel access to the 2-bit and the two 8- bit timeslots. 0: b-channel b/a does not access timeslot data b1, b2 or d, respectively. 1: b-channel b/a does access timeslot data b1, b2 or d, respectively. note: the terms b1/b2 should not imply that the 8-bit timeslots must be located in the first/second iom-2 timeslots, it ? s simply a placeholder for the 8-bit timeslot position selected in the registers bcha_tsdp_bc1/2 and bchb_tsdp_bc1/2. cs2-0 ... channel select this register is used to select one of eight iom channels. if enabled (en_d=1), the b- channel controller is connected to the 2-bit d-channel timeslot of that iom channel. 70 bchx_crdps_d 0 en_d en_ bc2 en_ bc1 cs2-0 rd/wr (51,52) register register address value after reset bcha_cr 51 h 08 h bchb_cr 52 h 81 h psb 2154 isdn module data sheet 264 2001-01-24 note: the reset value is determined by the channel select pins ch2-0 which are directly mapped to cs2-0. 5.8.4.7 dci_cr - control register for d and ci1 data (iom_cr.ci_cs=0) value after reset: a0 h dps_ci1 ... data port selection ci1 data 0: the ci1 data is output on dd and input from du 1: the ci1 data is output on du and input from dd en_ci1 ... enable ci1 data 0: ci1 data access is disabled 1: ci1 data access is enabled note: the timeslot for c/i1 cannot be programmed but is fixed to iom channel 1. d_en_d ... enable d-timeslot for d-channel controller d_en_b2 ... enable b2-timeslot for d-channel controller d_en_b1 ... enable b1-timeslot for d-channel controller these bits are used to select the timeslot length for the d-channel hdlc controller as it is capable to access not only the d-channel timeslot. the host can individually enable two 8-bit timeslots b1- and b2-channel (d_en_b1, d_en_b2) and one 2-bit timeslot d- channel (d_en_d) on iom-2. the position is selected via cs2-0. 0: d-channel controller does not access timeslot data b1, b2 or d, respectively 1: d-channel controller does access timeslot data b1, b2 or d, respectively for d-channel hdlc only (not for b-channel hdlc) the position of the two 8-bit timeslots is fixed to the first and second octett of the selected iom channel. cs2-0 ... channel select for d-channel controller this register is used to select one of eight iom channels. if enabled, the d-channel data is connected to the corresponding timeslot of that iom channel. 70 dci_cr dps_ ci1 en_ ci1 d_ en_d d_ en_b2 d_ en_b1 cs2-0 rd/wr (53) psb 2154 isdn module data sheet 265 2001-01-24 note: the reset value is determined by the channel select pins ch2-0 which are directly mapped to cs2-0. it should be noted that writing dci_cr.cs2-0 will also write to dcic_cr.cs2-0 and therefore modify the channel selection for the data of the c/i0 handler. 5.8.4.8 dcic_cr - control register for ci0 handler (iom_cr.ci_cs=1) value after reset: 00 h write access to this register is possible if iom_cr.ci_cs = 0 or iom_cr.ci_cs = 1. read access to this register is possible only if iom_cr.ci_cs = 1. dps_ci0 ... data port selection ci0 handler 0: the ci0 data is output on dd and input from du 1: the ci0 data is output on du and input from dd en_ci0 ... enable ci0 handler 0: ci0 data access is disabled 1: ci0 data access is enabled dps_d ... data port selection d-channel data 0: the d data is output on dd and input from du 1: the d data is output on du and input from dd cs2-0 ... channel select for c/i0 handler this register is used to select one of eight iom channels. if enabled, the data of the c/i0 handler is connected to the corresponding timeslots of that iom channel. the reset value is determined by the channel select pins ch2-0 which are mapped to cs2-0. 70 dcic_cr dps_ ci0 en_ ci0 dps_d 0 0 cs2-0 rd/wr (53) psb 2154 isdn module data sheet 266 2001-01-24 5.8.4.9 mon_cr - control register monitor data value after reset: 40 h for general information please refer to chapter 5.5.4 . dps ... data port selection 0: the monitor data is output on dd and input from du 1: the monitor data is output on du and input from dd en_mon ... enable output 0: the monitor data input and output is disabled 1: the monitor data input and output is enabled cs2-0 ... monitor channel selection 000: the monitor data is input/output on mon0 (3rd timeslot on iom-2) 001: the monitor data is input/output on mon1 (7th timeslot on iom-2) 010: the monitor data is input/output on mon2 (11th timeslot on iom-2) : 111: the monitor data is input/output on mon7 (31st timeslot on iom-2) note:the reset value is determined by the channel select pins ch2-0 which are directly mapped to cs2-0. 70 mon_cr dps en_ mon 0 0 0 cs2-0 rd/wr (54) psb 2154 isdn module data sheet 267 2001-01-24 5.8.4.10 sds_cr - control register serial data strobe value after reset: 00 h this register is used to select position and length of the strobe signal. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). for general information please refer to chapter 5.5.3 and chapter 5.5.3.2 . ens_tss ... enable serial data strobe of timeslot tss ens_tss+1 ... enable serial data strobe of timeslot tss+1 0: the serial data strobe signal sds is inactive during tss, tss+1 1: the serial data strobe signal sds is active during tss, tss+1 ens_tss+3 ... enable serial data strobe of timeslot tss+3 (d-channel) 0: the serial data strobe signal sds is inactive during the d-channel (bit7, 6) of tss+3 1: the serial data strobe signal sds is active during the d-channel (bit7, 6) of tss+3 tss ... timeslot selection selects one of 32 timeslots on the iom-2 interface (with respect to fsc) during which sds is active high or provides a strobed bcl clock output (see sds_conf.sds_bcl). the data strobe signal allows standard data devices to access a programmable channel. 70 sds_cr ens_ tss ens_ tss+1 ens_ tss+3 tss rd/wr (55) psb 2154 isdn module data sheet 268 2001-01-24 5.8.4.11 iom_cr - control register iom data value after reset: 08 h spu ... software power up 0: the du line is normally used for transmitting data 1: setting this bit to ? 1 ? will pull the du line to low. this will enforce connected layer 1 devices to deliver iom-clocking. after a subsequent ista.cic-interrupt (c/i-code change) and reception of the c/i-code ? pu ? (power up indication in te-mode) the microcontroller writes an ar or tim command as c/i-code in the cix0-register, resets the spu bit and waits for the following cic-interrupt. for general information please refer to chapter 5.5.7 . ci_cs ... c/i channel selection the channel selection for d-channel and c/i-channel is done in the channel select bits ch2-0 of register tr_cr (for the transceiver) and dci_cr (for the d-channel controller and c/i-channel controller). 0: a write access to cs2-0 has effect on the configuration of d- and c/i-channel, whereas a read access delivers the d-channel configuration only. 1: a write access to cs2-0 has effect on the configuration of the c/i-channel only, whereas a read access delivers the c/i-channel configuration only. tic_dis ... tic bus disable 0: the last octet of iom channel 2 (12th timeslot) is used as tic bus (te mode only). 1: the tic bus is disabled. the last octet of the last iom time slot (ts 11) can be used as every time slot. en_bcl ... enable bit clock bcl/sclk 0: the bcl/sclk clock is disabled 1: the bcl/sclk clock is enabled. 70 iom_cr spu 0 ci_cs tic_ dis en_ bcl clkm dis_ od dis_ iom rd/wr (57) psb 2154 isdn module data sheet 269 2001-01-24 clkm ... clock mode if the transceiver is disabled (dis_tr = ? 1 ? ) the dcl from the iom-2 interface is an input. 0: a double bit clock is connected to dcl 1: a single bit clock is connected to dcl for general information please refer to chapter 5.5 . dis_od ... disable open drain drivers 0: du/dd are open drain drivers 1: du/dd are push pull drivers dis_iom ... disable iom dis_iom should be set to ? 1 ? if external devices connected to the iom interface should be ? disconnected ? e.g. for power saving purposes or for not disturbing the internal iom connection between layer 1 and layer 2. however, the siuc-x internal operation between s-transceiver, b-channel and d-channel controller is independent of the dis_iom bit. 0: the iom interface is enabled 1: the iom interface is disabled (fsc, dcl clock outputs have high impedance; clock inputs are active; du, dd data line inputs are switched off and outputs have high impedance) 5.8.4.12 sti - synchronous transfer interrupt value after reset: 00 h for all interrupts in the sti register the following logical states are applied: 0: interrupt is not activated 1: interrupt is activated for general information please refer to chapter 5.5.1.1 . 70 sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 rd (58) psb 2154 isdn module data sheet 270 2001-01-24 stovxy ... synchronous transfer overflow interrupt enabled stov interrupts for a certain stixy interrupt are generated when the stixy has not been acknowledged in time via the ackxy bit in the asti register. this must be one (for dps= ? 0 ? ) or zero (for dps= ? 1 ? ) bcl clocks before the time slot which is selected for the stov. stixy ... synchronous transfer interrupt depending on the dps bit in the corresponding tsdpxy register the synchronous transfer interrupt stixy is generated two (for dps= ? 0 ? ) or one (for dps= ? 1 ? ) bcl clock after the selected time slot (tsdpxy.tss). note: st0vxy and ackxy are useful for synchronizing microcontroller accesses and receive/transmit operations. one bcl clock is equivalent to two dcl clock cycles. 5.8.4.13 asti - acknowledge synchronous transfer interrupt value after reset: 00 h for general information please refer to chapter 5.5.1.1 . ackxy ... acknowledge synchronous transfer interrupt after an stixy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ackxy bit to ? 1 ? . 5.8.4.14 msti - mask synchronous transfer interrupt value after reset: ff h 70 asti 0000ack 21 ack 20 ack 11 ack 10 wr (58) 70 msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 rd/wr (59) psb 2154 isdn module data sheet 271 2001-01-24 for the msti register the following logical states are applied: 0: interrupt is not masked 1: interrupt is masked for general information please refer to chapter 5.5.1.1 . stovxy ... synchronous transfer overflow for stixy mask bits for the corresponding stovxy interrupt bits. stixy ... synchronous transfer interrupt xy mask bits for the corresponding stixy interrupt bits. 5.8.4.15 sds_conf - configuration register for serial data strobes value after reset: 00 h for general information on sds_bcl please refer to chapter 5.5.3 . diom_inv ... du/dd on iom timeslot inverted 0:du/dd are active during sds high phase and inactive during the low phase. 1:du/dd are active during sds low phase and inactive during the high phase. this bit has only effect if diom_sds is set to ? 1 ? otherwise diom_inv is don ? t care. diom_sds ... du/dd on iom controlled via sds 0: the pin sds and its configuration settings are used for serial data strobe only. the iom-2 data lines are not affected. 1: the du/dd lines are deactivated during the during high/low phase (selected via diom_inv) of the sds signal. the sds timeslot is selected in sds_cr. sds_bcl ... enable iom bit clock for sds 0: the serial data strobe is generated in the programmed timeslot. 1: the iom bit clock is generated in the programmed timeslot. 70 sds_ conf 0000diom_ inv diom_ sds 0sds_ bcl rd/wr (5a) psb 2154 isdn module data sheet 272 2001-01-24 5.8.4.16 mcda - monitoring cda bits value after reset: ff h mcdaxy ... monitoring cdaxy bits bit 7 and bit 6 of the cdaxy registers are mapped into the mcda register. this can be used for monitoring the d-channel bits on du and dd and the ? echo bits ? on the tic bus with the same register 5.8.4.17 mor - monitor receive channel value after reset: ff h contains the monitor data received in the iom-2 monitor channel according to the monitor channel protocol. the monitor channel (0-7) can be selected by setting the monitor channel select bit mon_cr.mcs. 5.8.4.18 mox - monitor transmit channel value after reset: ff h contains the monitor data to be transmitted in iom-2 monitor channel according to the monitor channel protocol.the monitor channel (0-7) can be selected by setting the monitor channel select bit mon_cr.mcs. 70 mcda mcda21 mcda20 mcda11 mcda10 rd (5b) bit7 bit6 bit7 bit6 bit7 bit6 bit7 bit6 70 mor monitor receiver data rd (5c) 70 mox monitor transmit data wr (5c) psb 2154 isdn module data sheet 273 2001-01-24 5.8.4.19 mosr - monitor interrupt status register value after reset: 00 h mdr ... monitor channel data received mer ... monitor channel end of reception mda ... monitor channel data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab ... monitor channel data abort 5.8.4.20 mocr - monitor control register value after reset: 00 h mre ... monitor receive interrupt enable 0: monitor interrupt status mdr generation is masked 1: monitor interrupt status mdr generation is enabled mrc ... mr bit control determines the value of the mr bit: 0: mr is always ? 1 ? . in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mre = 1). 1: mr is internally controlled by the siuc-x according to monitor channel protocol. in addition, the mdr interrupt is enabled for all received bytes according to the monitor channel protocol (if mre = 1). 70 mosr mdr mer mda mab 0 0 0 0 rd (5d) 70 mocr mre mrc mie mxc 0 0 0 0 rd/wr (5e) psb 2154 isdn module data sheet 274 2001-01-24 mie ... monitor interrupt enable monitor interrupt status mer, mda, mab generation is enabled (1) or masked (0). mxc ... mx bit control determines the value of the mx bit: 0:the mx bit is always ? 1 ? . 1:the mx bit is internally controlled by the siuc-x according to monitor channel protocol. 5.8.4.21 msta - monitor status register value after reset: 00 h mac ... monitor transmit channel active the data transmisson in the monitor channel is in progress. tout ... time-out read-back value of the tout bit. 5.8.4.22 mconf - monitor configuration register value after reset: 00 h tout... time-out 0: the monitor time-out function is disabled 1: the monitor time-out function is enabled msta 00000mac0tout rd (5f) mconf0000000tout wr (5f) psb 2154 isdn module data sheet 275 2001-01-24 5.8.5 interrupt and general configuration 5.8.5.1 ista - interrupt status register value after reset: 00 h for all interrupts in the ista register following logical states are applied: 0: interrupt is not acitvated 1: interrupt is acitvated ica, icb, icd ... hdlc interrupt from b-channel a, b or d-channel an interrupt originated from the hdlc controllers of b-channel a, b or of the d-channel has been recognized. st ... synchronous transfer this interrupt is generated to enable the microcontroller to lock on to the iom timing for synchronous transfers. the source can be read from the sti register. cic ... c/i channel change a change in c/i channel 0 or c/i channel 1 has been recognized. the actual value can be read from cir0 or cir1. aux ... auxiliary interrupts singals an interrupt generated from external awake (pin eaw ), watchdog timer overflow, timer2, timer3 or from one of the interrupt input pins (int1 , int2 ). the source can be read from the auxiliary interrupt register auxi. tran ... transceiver interrupt an interrupt originated in the transceiver interrupt status register (istatr) has been recognized. mos ... monitor status a change in the monitor status register (mosr) has occured. note: a read of the ista register clears none of the interrupts. they are only cleared by reading the corresponding status register. 70 ista ica icb st cic aux tran mos icd rd (60) psb 2154 isdn module data sheet 276 2001-01-24 5.8.5.2 ista_init - interrupt status register initialize value after reset: ff h after reset all interrupts from the isdn module are disabled. in order to enable the isdn interrrupt status register (ista) to generate interrupts to the microcontroller, the ista_init register must be set to 00 h . this value should not be changed again afterwards during normal operation. enabling and disabling of certain isdn interrupts from ista should be done in the interrupt enable registers of the microcontroller ien0, ien1 and ien2 (see chapter 6.1.2 ). 5.8.5.3 auxi - auxiliary interrupt status register value after reset: 00 h for all interrupts in the ista register following logical states are applied: 0: interrupt is not acitvated 1: interrupt is acitvated eaw ... external awake interrupt an interrupt from the eaw pin has been detected. wov ... watchdog timer overflow signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits wtc1 and wtc2 (mode1 register) in the correct manner. a reset pulse has been generated by the siuc-x. tin3, 2 ... timer interrupt 3, 2 an interrupt originated from timer 2 or timer 3 is recognized, i.e the timer has expired. 70 ista_init wr (60) 70 auxi 0 0 eaw wov tin3 tin2 int2 int1 rd (61) psb 2154 isdn module data sheet 277 2001-01-24 int2, 1 ... auxiliary interrupt from external devices 2, 1 a low level or a negative state transition (programmable in acfg2.el2/1) is detected at pin aux7 or aux6, respectively. 5.8.5.4 auxm - auxiliary mask register value after reset: ff h for the auxiliary mask register following logical states are applied: 0: interrupt is enabled 1: interrupt is disabled each interrupt source in the auxi register can selectively be masked/disabled by setting the corresponding bit in auxm to ? 1 ? . masked interrupt status bits are not indicated when auxi is read. instead, they remain internally stored and pending, until the mask bit is reset to ? 0 ? . 5.8.5.5 mode1 - mode1 register value after reset: 00 h wtc1, 2 ... watchdog timer control 1, 2 after the watchdog timer mode has been selected (rss = ? 11 ? ) the watchdog timer is started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bit in the following sequence to reset and restart the watchdog timer, i.e. in order to reset the timer again the c has to make 2 write accesses to wtc1,2 after every 128 ms period. 70 auxm 1 1 eaw wov tin3 tin2 int2 int1 wr (61) 70 mode1 0 0 0 wtc1 wtc2 cfs rss2 rss1 rd/wr (62) wtc1 wtc2 1. 2. 1 0 0 1 psb 2154 isdn module data sheet 278 2001-01-24 if wtc1/2 is not written fast enough in this way, the timer expires and a wov-interrupt (auxi register) together with a reset pulse is generated. cfs ... configuration select this bit determines clock relations and recovery on s/t and iom interfaces. 0: the iom interface clock and frame signals are always active, "power down" state included. the states "power down" and "power up" are thus functionally identical except for the indication: pd = 1111 and pu = 0111. with the c/i command timing (tim) the microcontroller can enforce the "power up" state and with c/i command deactivation indication (di) the "power down" state is reached again. however, it is also possible to activate the s-interface directly with the c/i command activate request (ar 8/10/l) without the tim command. 1: the iom interface clock and frame signals are normally inactive ("power down"). for activating the iom-2 clocks the "power up" state can be induced by software (iom_cr.spu) or by resetting cfs again. after that the s-interface can be activated with the c/i command activate request (ar 8/10/l). the "power down" state can be reached again with the c/i command deactivation indication (di). note: after reset the iom interface is always active. to reach the "power down" state the cfs-bit has to be set. for general information please refer to chapter 5.2.9 . rss2, rss1... reset source selection 2,1 the siuc-x reset sources and the sds functionality for the sds/rsto output pin can be selected according to the table below. rss c/i code change eaw watchdog timer sds functionality bit 1 bit 0 0 0 -- -- -- -- 0 1 -- -- -- x 1 0 x x -- -- 11 -- -- x -- psb 2154 isdn module data sheet 279 2001-01-24 if rss = ? 00 ? no above listed reset source is selected and therefore no reset is generated at sds/rsto . if rss = ? 01 ? the sds/rsto pin has sds functionality and a serial data strobe signal is output at the sds/rsto pin. in this mode no reset is output at sds/rsto . watchdog timer after the selection of the watchdog timer (rss = ? 11 ? ) the timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bits in two consecutive bit pattern (see description above of the wtc1, 2 bits) otherwise the watchdog timer expires and a reset pulse of 125 s t 250 s is generated. once rss1,2 is programmed to ? 11 ? the value cannot be reprogrammed to any other value, i.e. deactivation of the watchdog timer is only possible with a hardware reset. if rss = ? 10 ? is selected the following two reset sources generate a reset pulse of 125 s t 250s at the sds/rsto pin: - external (subscriber) awake (eaw ) the eaw input pin serves as a request signal from the subscriber to initiate the awake function in a terminal and generates a reset pulse (in te mode only). - exchange awake (c/i code) a c/i code change generates a reset pulse. after a reset pulse generated by the siuc-x and the corresponding interrupt (wov or cic) the actual reset source can be read from the ista. 5.8.5.6 id - identification register value after reset: 01 h design ... design number the design number allows to identify different hardware designs of the siuc-x by software. 01 h : version 1.3 (all other codes reserved) 70 id 0 0 design rd (64) psb 2154 isdn module data sheet 280 2001-01-24 5.8.5.7 sres - software reset register value after reset: 00 h res_xx ... reset functional block xx a reset can be activated on the functional block c/i-handler, b-channel a and b, monitor channel, d-channel, iom handler, s-transceiver and to pin rsto . setting one of these bits to ? 1 ? causes the corresponding block to be reset for a duration of 4 bcl clock cycles, except res_rsto which is activated for a duration of 125 ... 250s. the bits are automatically reset to ? 0 ? again. 5.8.5.8 timr3 - timer 3 register value after reset: 00 h tmd ... timer mode timer 3 can be used in two different modes of operation. 0: count down timer. an interrupt is generated only once after a time period of 1 ... 63 ms. 1: periodic timer. an interrupt is periodically generated every 1 ... 63 ms (see cnt). cnt ... timer counter 0: timer off. 1 ... 63: timer period = 1 ... 63 ms by writing ? 0 ? to cnt the timer is immediately stopped. a value different from that determines the time period after which an interrupt will be generated. if the timer is already started with a certain cnt value and is written again before an interrupt has been released, the timer will be reset to the new value and restarted again. an interrupt is indicated to the host in auxi.tin3. 70 sres res_ ci res_ bcha res_ bchb res_ mon res_ dch res_ iom res_ tr res_ rsto wr (64) 70 timr3 tmd 0 cnt rd/wr (65) psb 2154 isdn module data sheet 281 2001-01-24 note: reading back this value delivers back the current counter value which may differ from the programmed value if the counter is running. 5.8.6 b-channel registers the registers for b-channel a are contained in the address space 70 h - 7a h and for b- channel b in the address space 80 h - 8a h . 5.8.6.1 istab - interrupt status register b-channels value after reset: 10 h for general information please refer to chapter 5.6.6 . rme ... receive message end one complete frame of length less than or equal to the defined block size (exmb.rfbs) or the last part of a frame of length greater than the defined block size has been received. the contents are available in the rfifob. the message length and additional information may be obtained from rbchb and rbclb and the rstab register. rpf ... receive pool full a data block of a frame longer than the defined block size (exmb.rfbs) has been received and is available in the rfifob. the frame is not yet complete. rfo ... receive frame overflow the received data of a frame could not be stored, because the rfifob is occupied. the whole message is lost. this interrupt can be used for statistical purposes and indicates that the microcontroller does not respond quickly enough to an rpf or rme interrupt (istab). xpr ... transmit pool ready a data block of up to the defined block size 32 or 64 (exmb.xfbs) can be written to the xfifob. 70 istab rme rpf rfo xpr 0 xdu 0 0 rd (70/80) psb 2154 isdn module data sheet 282 2001-01-24 an xpr interrupt will be generated in the following cases: after an xtf or xme command as soon as the 32 or 64 bytes in the xfifob are available and the frame is not yet complete after an xtf together with an xme command is issued, when the whole frame has been transmitted after a reset of the transmitter (xres) after a device reset xdu ... transmit data underrun the current transmission of a frame is aborted by transmitting seven ? 1 ? s because the xfifob holds no further data. this interrupt occurs whenever the microcontroller has failed to respond to an xpr interrupt (istab register) quickly enough, after having initiated a transmission and the message to be transmitted is not yet complete. 5.8.6.2 maskb - mask register b-channels value after reset: ff h each interrupt source in the istab register can selectively be masked by setting the corresponding bit in maskb to ? 1 ? . masked interrupt status bits are not indicated when istab is read. instead, they remain internally stored and pending until the mask bit is reset to ? 0 ? . for general information please refer to chapter 5.6.6 . 70 maskb rme rpf rfo xpr 1 xdu 1 1 wr (70/80) psb 2154 isdn module data sheet 283 2001-01-24 5.8.6.3 starb - status register b-channels value after reset: 40 h xdov ... transmit data overflow more than 16 or 32 bytes (according to selected block size) have been written to the xfifob, i.e. data has been overwritten. xfw ... transmit fifo write enable data can be written to the xfifob. this bit may be polled instead of (or in addition to) using the xpr interrupt. raci ... receiver active indication the b-channel hdlc receiver is active when raci = ? 1 ? . this bit may be polled. the raci bit is set active after a begin flag has been received and is reset after receiving an abort sequence. xaci ... transmitter active indication the b-channel hdlc-transmitter is active when xaci = ? 1 ? . this bit may be polled. the xaci-bit is active when an xtf-command is issued and the frame has not been completely transmitted. 70 starb xdov xfw 0 0 raci 0 xaci 0 rd (71/81) psb 2154 isdn module data sheet 284 2001-01-24 5.8.6.4 cmdrb - command register b-channels value after reset: 00 h rmc ... receive message complete reaction to rpf (receive pool full) or rme (receive message end) interrupt. by setting this bit, the microcontroller confirms that it has fetched the data, and indicates that the corresponding space in the rfifob may be released. rres ... receiver reset hdlc receiver is reset, the rfifob is cleared of any data. xtf ... transmit transparent frame after having written up to 32 or 64 bytes (exmb.xfbs) to the xfifob, the microcontroller initiates the transmission of a transparent frame by setting this bit to ? 1 ? . the opening flag is automatically added to the message by the siuc-x. xme ... transmit message end by setting this bit to ? 1 ? the microcontroller indicates that the data block written last to the xfifob completes the corresponding frame. the siuc-x terminates the transmission by appending the crc (if exmb.xcrc=0) and the closing flag sequence to the data. xres ... transmitter reset the b-channel hdlc transmitter is reset and the xfifob is cleared of any data. this command can be used by the microcontroller to abort a frame currently in transmission. note: after an xpr interrupt further data has to be written to the xfifob and the appropriate transmit command (xtf) has to be written to the cmdrb register again to continue transmission, when the current frame is not yet complete (see also xpr in istab). during frame transmission, the 0-bit insertion according to the hdlc bit-stuffing mechanism is done automatically. 70 cmdrb rmc rres 0 0 xtf 0 xme xres wr (71/81) psb 2154 isdn module data sheet 285 2001-01-24 5.8.6.5 modeb - mode register value after reset: c0 h mds2-0 ... mode select determines the message transfer mode of the hdlc controller, as follows: note: - rah1, rah2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); group address= fixed value fc / fe h . - ral1, ral2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; group address= fixed value ff h . 70 modeb mds2 mds1 mds0 0 rac 0 0 0 rd/wr (72/82) mds2-0 mode number of address bytes address comparison remark 1.byte 2.byte 0 0 0reserved 0 0 1reserved 0 1 0non-auto mode 1ral1,ral2 ? one-byte address compare. 0 1 1non-auto mode 2 rah1,rah2, group address ral1,ral2, group address two-byte address compare. 1 0 0extended transparent mode 1 1 0transparent mode 0 ?? ? no address compare. all frames accepted. 1 1 1transparent mode 1 > 1 rah1,rah2, group address ? high-byte address compare. 1 0 1transparent mode 2 > 1 ? ral1,ral2, group address low-byte address compare. psb 2154 isdn module data sheet 286 2001-01-24 rac ... receiver active the b-channel hdlc receiver is activated when this bit is set to ? 1 ? . if set to ? 0 ? the hdlc data is not evaluated in the receiver. 5.8.6.6 exmb - extended mode register b-channels value after reset: 00 h xfbs ? transmit fifo block size 0 ? block size for the transmit fifo data is 64 byte 1 ? block size for the transmit fifo data is 32 byte note: a change of xfbs will take effect after a receiver command (cmdrb.xme, cmdrb.xres, cmdrb.xtf) has been written. rfbs ? receive fifo block size note: a change of rfbs will take effect after a transmitter command (cmdrb.rmc, cmdrb.rres,) has been written sra ? store receive address 0 ? receive address is not stored in the rfifob 1 ? receive address is stored in the rfifob 70 exmb xfbs rfbs sra xcrc rcrc 0 itf rd/wr (73/83) rfbs block size receive fifo bit 6 bit5 0 0 64 byte 0 1 32 byte 1 0 16 byte 118 byte psb 2154 isdn module data sheet 287 2001-01-24 xcrc ? transmit crc 0 ? crc is transmitted 1 ? crc is not transmitted rcrc ? receive crc 0 ? crc is not stored in the rfifob 1 ? crc is stored in the rfifob itf ? interframe time fill selects the inter-frame time fill signal which is transmitted between hdlc-frames. 0 ? idle (continuous ? 1 ? ) 1 ? flags (sequence of patterns: ? 0111 1110 ? ) 5.8.6.7 rah1 - rah1 register value after reset: 00 h rah1 ... value of the first individual programmable high address byte in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individual programmable values in rah1, rah2 or group address fc h /fe h . mha ... mask high address 0: the rah1 address of an incoming frame is compared with rah1, rah2 and group address. 1: the rah1 address of an incoming frame is compared with rah1 and group address. rah1 can be masked with rah2 thereby bitpositions of rah1 are not compared if they are set to ? 1 ? in rah2. 5.8.6.8 rah2 - rah2 register value after reset: 00 h 70 rah1 rah1 0 mha wr (75/85) 70 rah2 rah2 0 mla wr (76/86) psb 2154 isdn module data sheet 288 2001-01-24 rah2 ... value of the second individual programmable high address byte see rah1 register above. rah1 and rah2 are used in non-auto mode when a 2-byte address field has been selected and in the transparent mode 1. mla ... mask low address 0: the address of an incoming frame is compared with ral1, ral2 and group address. 1: the address of an incoming frame is compared with ral1 and group address. ral1 can be masked with ral2 thereby bitpositions of ral1 are not compared if they are set to ? 1 ? in ral2. 5.8.6.9 rbclb - receive frame byte count low b-channels value after reset: 00 h rbc7-0 ... receive byte count eight least significant bits of the total number of bytes in a received message (see rbchb register). 70 rbclb rbc7 rbc0 rd (76/86) psb 2154 isdn module data sheet 289 2001-01-24 5.8.6.10 rbchb - receive frame byte count high b-channels value after reset: 00 h . ov ... overflow a ? 1 ? in this bit position indicates a message longer than (2 12 - 1) = 4095 bytes . rbc8-11 ... receive byte count four most significant bits of the total number of bytes in a received message (see rbclb register). note: normally rbchb and rbclb should be read by the microcontroller after an rme- interrupt in order to determine the number of bytes to be read from the rfifob, and the total message length. the contents of the registers are valid only after an rme or rpf interrupt, and remain so until the frame is acknowledged via the rmc bit or rres. 5.8.6.11 ral1 - ral1 register 1 value after reset: 00 h ral1 ... receive address byte low register 1 the general function (read/write) and the meaning or contents of this register depends on the selected operating mode: ? non-auto mode (16-bit address): ral1 can be programmed with the value of the first individual low address byte. ? non-auto mode (8-bit address): according to x.25 lapb protocol, the address in ral1 is recognized as command address. 70 rbchb 0 0 0 ov rbc11 rbc8 rd (77/87) 70 ral1 ral1 wr (77/87) psb 2154 isdn module data sheet 290 2001-01-24 5.8.6.12 ral2 - ral2 register value after reset: 00 h ral2 ... receive address byte low register 2 value of the second individual programmable low address byte. if a one byte address field is selected, ral2 is recognized as response according to x.25 lapb protocol. 5.8.6.13 rstab - receive status register b-channels value after reset: 0e h vfr... valid frame determines whether a valid frame has been received. the frame is valid (1) or invalid (0). a frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). rdo ... receive data overflow if rdo=1, at least one byte of the frame has been lost, because it could not be stored in rfifob. as opposed to istab.rfo an rdo indicates that the beginning of a frame has been received but not all bytes could be stored as the rfifob was temporarily full. crc ... crc check the crc is correct (1) or incorrect (0). rab ... receive message aborted the receive message was aborted by the remote station (1), i.e. a sequence of seven 1 ? s was detected before a closing flag. 70 ral2 ral2 wr (78/88) 70 rstab vfr rdo crc rab ha1 ha0 c/r la rd (78/88) psb 2154 isdn module data sheet 291 2001-01-24 ha1, ha0 ? high byte address compare; significant only in non automode 16 and in transparent mode 1 in operating modes which provide high byte address recognition, the siuc-x compares the high byte of a 2-bytes address with the contents of two individual programmable registers (rah1, rah2) and the fixed values fe h and fc h (group address). depending on the result of this comparison, the following bit combinations are possible: 10 ? rah1 has been recognized 00 ? rah2 has been recognized 01 ? group address has been recognized c/r ... command/response the c/r bit contains the c/r bit of the received frame (bit1 in the sapi address, lapd). la ? low byte address compare; significant only in non automodes 8 and 16 and in transparent mode 2 the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two programmable registers (ral1, ral2) and with the group address (fixed value ff h ) 0 ? group address has been recognized 1 ? ral1 or ral2 has been recognized note: rstab corresponds to the last received hdlc frame; it is duplicated into rfifob for every frame (last byte of frame). if several frames are contained in the rfifob the corresponding status information for each frame should be evaluated from the fifo contents (last byte) as rstab only refers to last frame in the fifo. 5.8.6.14 tmb -test mode register b-channels value after reset: 00 h tlp ... test loop the tx path of layer-2 is internally connected with the rx path of layer-2. data coming from the layer 1 controller will not be forwarded to the layer 2 controller. 70 tmb 0000000tlp rd/wr (79/89) psb 2154 isdn module data sheet 292 2001-01-24 5.8.6.15 rfifob - receive fifo b-channels a read access to this register gives access to the ? current ? fifo location selected by an internal pointer which is automatically incremented after each read access. the rfifob contains up to 128 bytes of received data. after an istab.rpf interrupt, a complete data block is available. the block size can be 8, 16, 32 or 64 bytes depending on the exmb.rfbs setting. after an istab.rme interrupt, the number of received bytes can be obtained by reading the rbclb register. 5.8.6.16 xfifob - transmit fifo b-channels a write access to this register gives access to the ? current ? fifo location selected by an internal pointer which is automatically incremented after each write access. depending on exmb.xfbs up to 32 or 64 bytes of transmit data can be written to the xfifob following an istab.xpr interrupt. 70 rfifob receive data rd (7a/8a) 70 xfifob transmit data wr (7a/8a) psb 2154 interrupt system data sheet 293 2001-01-24 6 interrupt system the siuc-x provides 14 interrupt sources with 4 priority levels. 13 interrupts can be generated by the onchip peripherals (timer0, timer1, usb module, isdn module), and 1 interrupt may be triggered externally (p3.1/int0 ). further interrupt sources are combined in the isdn registers (e.g. interrupts from level detect, watchdog, timers and external interrupts, see figure 115 ). figure 111 , figure 112 , figure 113 and figure 114 give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections. figure 111 interrupt request sources (part 1) - miscellaneous interrupts some of the interrupts can wakeup the siuc from suspend mode ( chapter 3.7.5 ). however, in suspend mode the int0 interrupt is directly routed to the nmi interrupt, i.e. the ien0.ex0 bit has only effect on the generation of the int0 interrupt in operational and idle mode, but not is suspend mode (see chapter 6.3 for wakeup from suspend). tf0 et0 tcon.5 000b h ien0.1 ip1.1, ip0.1 tf1 et1 tcon.7 001b h ien0.3 ip1.3, ip0.3 ie0 ex0 tcon.1 0003 h ien0.0 ip1.0, ip0.0 > 1 it0 tcon.0 eal ien0.7 timer 0 overflow timer 1 overflow p3.1 / int0 low priority high priority 2154_20.vsd request flag is cleared by hardware epcint es eepint.0 0023 h ien0.4 ip1.4, ip0.4 eeprom transaction psb 2154 interrupt system data sheet 294 2001-01-24 figure 112 interrupt request sources (part 2) - usb endpoint interrupts 2154_21.vsd request flag is cleared by hardware after the corresponding register has been read ack0 aie0 epir0.7 epie0.7 nack0 naie0 epir0.6 epie0.6 rle0 rleie0 epir0.5 epie0.5 dnr0 dnrie0 epir0.3 epie0.3 nod0 nodie0 epir0.2 epie0.2 eod0 eodie0 epir0.1 epie0.1 sod0 sodie0 epir0.0 epie0.0 > 1 epi0 gepir.0 gepie0 epbc0.4 endpoint 0 interrupts endpoint 1 interrupts endpoint 2 interrupts endpoint 3 interrupts endpoint 4 interrupts endpoint 5 interrupts endpoint 6 interrupts endpoint 7 interrupts endpoint interrupts 0033 h ip1.0 ip0.0 > 1 ex6 ien1.0 low priority high priority eal ien0.7 psb 2154 interrupt system data sheet 295 2001-01-24 figure 113 interrupt request sources (part 3) - usb device interrupts se0i se0ie dirr.7 002b h ip1.5 ip0.5 ex5 ien0.5 2154_22.vsd request flag is cleared by hardware after the corresponding register has been read dier.5 sbi sbie dirr.4 dier.4 sei seie dirr.3 dier.3 sti stie dirr.2 dier.2 sui suie dirr.1 dier.1 sofi sofie dirr.0 dier.0 device interrupts low priority high priority dier.6 ddi ddie dirr.5 dier.7 dai daie dirr.6 eal ien0.7 drvi drvie ciari.0 ciarie.0 gsir gsie dsir.0 dsir.1 > 1 psb 2154 interrupt system data sheet 296 2001-01-24 figure 114 interrupt request sources (part 4) - isdn interrupts ica ex7 ista.7 003b h ien1.1 ip1.1 ip0.1 eal ien0.7 b-channel hdlc a low priority high priority 2154_23.vsd request flag is cleared by hardware after the corresponding status register has been read. a read of ista clears only the aux interrupt icd ex8 ista.0 0043 h ien1.2 ip1.2 ip0.2 d-channel hdlc st ex9 ista.5 004b h ien1.3 ip1.3 ip0.3 synchronous transfer mos ex10 ista.1 0053 h ien1.4 ip1.4 ip0.4 monitor status tran ex11 ista.2 005b h ien1.5 ip1.5 ip0.5 transceiver cic ex12 ista.4 0063 h ien2.0 ip1.0 ip0.0 ci channel change icb ex13 ista.6 006b h ien2.1 ip1.1 ip0.1 b-channel hdlc b aux ex14 ista.3 0083 h ien2.2 ip1.2 ip0.2 auxiliary psb 2154 interrupt system data sheet 297 2001-01-24 special events in the isdn part are indicated by means of eight interrupt outputs (ica, icb, st, cic, aux, tran, mos, icd), which request the c to read status information or transfer data from/to the isdn registers. the cause of an interrupt must be determined by the c by reading the corresponding interrupt status registers. for all eight individual interrupt sources the c can read one interrupt status register (ista) to determine the source. the structure of the isdn interrupt status registers is shown in figure 115 . figure 115 isdn interrupt status registers the eight interrupts point at interrupt sources in the d-channel hdlc controller (icd), b-channel hdlc controllers (ica, icb), monitor- (mos) and c/i- (cic) handler, the transceiver (tran), the synchronous transfer (st) and the auxiliary interrupts (auxi). the isdn interrupts from ista are enable/disabled in the ien1 and ien2 registers, however after reset the ista_init register must be set to 00h in order to enable isdn interrupts. icd mos tran aux cic st icb ica icd mos tran aux cic st icb ica sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 istab sti ack10 ack11 ack20 ack21 asti xdu xpr rfo rpf rme xdu xpr rfo rpf rme xdu xpr rfo rpf rme xdu xpr rfo rpf rme maskb msti ci1e cic1 cic0 cir0 cix1 xdu xmr xpr rfo rpf rme maskd xdu xmr xpr rfo rpf rme istad mie mre mab mda mer mdr sqw sqc ric ld masktr istatr sqw sqc ric ld ien1 ien2 ista 2154_48 interrupts istab maskb b-channel a b-channel b mocr mosr int1 int2 tin1 tin2 wov auxm auxi int1 int2 tin1 tin2 wov eaw eaw d-channel psb 2154 interrupt system data sheet 298 2001-01-24 6.1 interrupt registers 6.1.1 interrupt request / control flags the external interrupt 0 (int0 ) can be either level-activated or negative transition activated, depending on bit it0 in register tcon. the flag that generates this interrupt is bit ie0 in tcon. when the external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to, but only if the interrupt was transition-activated. if the interrupt was level-activated, then the requesting external source directly controls the request flag, rather than the onchip hardware. the timer 0 and timer 1 interrupts are generated by tf0 and tf1 in register tcon, which are set by a rollover in their respective timer/counter registers. when a timer interrupt is generated, the flag that generated it is cleared by the onchip hardware when the service routine is vectored to. 6.1.1.1 tcon - timer control register resetvalue:00 h address: 88 h note: the shaded bits are not used for interrupt control. 76543210 tf1 tr1 tf0 tr0 0 0 ie0 it0 rrwrrwrrwrrw bit function tf1 timer 1 overflow flag set by hardware when timer/counter 1 overflow. cleared by hardware when processor calls the interrupt service routine. tr1 timer 1 run control if 1, timer runs; if 0, timer is halted. tf0 timer 0 overflow flag set by hardware when timer/counter 0 overflow. cleared by hardware when processor calls the interrupt service routine. tr0 timer 0 run control if 1, timer runs; if 0, timer is controlled by int0 and gate0. psb 2154 interrupt system data sheet 299 2001-01-24 6.1.1.2 eepint - eeprom interrupt control register resetvalue:00 h address: 93 h 6.1.1.3 dirr - usb device interrupt request register resetvalue:00 h address: c4 h for accessing dirr, the sfr epsel must be 80 h . the usb device interrupt request register contains the device specific interrupt flags of the usb module. these flags are set after the occurrence of special events. if a request flag is set, it is automatically cleared after a read operation of the dirr register. the interrupts contained in the dirr register can individually be masked in the dier register. ie0 external interrupt 0 edge flag (pin int0 ) set by hardware when an external interrupt condition at pin int0 is detected (low level if it0=0 or falling edge if it0=1). it0 interrupt 0 control bit (pin int0 ) if 1, a falling edge triggers an interrupt; if 0, a low level triggers an interrupt. 76543 210 00000 00epcint r r r r r r r rw bit function epcint eeprom control interrupt this bit is set when an eeprom transaction, which is started by setting the esta bit in the eepsl register, is finished. the microcontroller has to acknowledge this bit by writing a ? 0 ? to it. 76543210 se0i dai ddi sbi sei sti sui sofi rrrrrrrr psb 2154 interrupt system data sheet 300 2001-01-24 the register epirn (n=0-7) contains usb endpoint specific interrupt request flags. this sfr is available for each endpoint. if a request flag in epirn is set, it is automatically cleared after a read operation of the epirn register. bit function se0i single ended zero interrupt se0i is set each time a single ended zero is detected for equal or greater than 2.5 s. eop (2 bit times) is not detected. dai device attached interrupt bit dai is automatically set after detection of the usb device being attached to the usb bus (for further information see chapter 4.8 ). ddi device detached interrupt bit ddi is automatically set after detection of the device being detached from the usb bus (for further information see chapter 4.8 ). sbi suspend begin interrupt sbi is automatically set when the suspend mode is entered. sei suspend end interrupt sei is automatically set when the suspend mode is left. sti status interrupt sti is set if the host requires a status transfer and the device answers with nack (if bit esp is set, the device answers with ack and then sti is not set). sui setup interrupt sui is automatically set after a successful reception of a setup packet which is not handled by the usb module and must be forwarded to the cpu. the setup packet itself is limited to 8 bytes and stored at usb memory addresses 00h to 07h. if a setup interrupt occurs, the control and status bits ubf0, cbf0, sod0 and dir0 in the endpoint registers epbs0 and epir0 are cleared. dir0=0 predicts the direction of the next usb access (data phase) to be from host to cpu. bit dir0 is automatically set (cpu to host), if the host tries to perform a read access in the first data packet. sofi start of frame interrupt sof is automatically set after detection of a start of frame packet on the usb. psb 2154 interrupt system data sheet 301 2001-01-24 6.1.1.4 dsir - device setup interrupt register this register can only be accessed when the endpoint select register (adr. d2 h ) is set to epsel = 80 h . resetvalue:00 h address: c5 h a read access to the dsir register will clear a gsir interrupt request. this interrupt is generated for all usb standard device requests (see chapter 4.6.3 ). 6.1.1.5 epirn - endpoint interrupt request register reset value epir0: 01 h , reset value epir1-epir7: 00 h address: c4 h for accessing epirn, the sfr epsel must be 0n h . the interrupts contained in the epirn register can individually be masked in the epien register. 76543210 000000gsiegsir rrrrrrrwr bit function gsie global setup packet interrupt enable 0: interrupt generation is disabled 1: interrupt generation is enabled gsir global setup packet interrupt request a setup packet has been received. 76543210 ackn nackn rlen 0 dnrn nodn eodn sodn rrrrrrrr psb 2154 interrupt system data sheet 302 2001-01-24 in dual buffer mode, bits sodn and eodn can be set simultaneously if the corresponding buffer page is swapped. bit function ackn usb acknowledge bit ackn=1 indicates a successful action on the usb. nackn usb not acknowledge bit nack is set for all unsuccessful actions on the usb. rlen read length error bit rlen is automatically set if the number of bytes read by the usb does not correspond to the packet length programmed by the cpu. dnrn data not ready this bit is set by hardware if the usb module requires an access to usb memory, but no buffer is available. usb read action: dnrn is set if ubf is not set. usb write action: dnrn is set if ubf is set. nodn no data this bit indicates an incorrect cpu read or write access to usb memory. it is set if the cpu processes a read access to an empty usb buffer or a write access to a full buffer. nodn is also set if the direction is write (dirn=0 for usb write access) and the cpu tries to write to the usb memory buffer. eodn end of data during a usb read access eodn is set if the cpu has written a programmable number (maxlen) of bytes in the transmit buffer. as a result, the buffer is full and no more write actions from the cpu are allowed. during a usb write access eodn is set if the cpu has read a programmable number (usblen) of bytes out of the receive buffer. as a result, the buffer is empty now and no more read actions from the cpu are allowed. sodn start of data during a usb read access sodn is set if the usb has read a fixed number (usblen) of bytes from the transmit buffer. as a result, the buffer is now empty and the cpu can process write actions again. during a usb write access sodn is set if the usb has written a fixed number (usblen) of bytes to the receive buffer. as a result, the buffer is full and the cpu can start read actions. psb 2154 interrupt system data sheet 303 2001-01-24 6.1.1.6 gepir - global endpoint interrupt request register the global endpoint interrupt request register gepir contains one flag for each endpoint which indicates whether one or more of the seven endpoint specific interrupt requests has become active. if a request flag in gepir is set, it is automatically cleared after a read operation of the gepir register. resetvalue:00 h address: d6 h 76543210 epi7 epi6 epi5 epi4 epi3 epi2 epi1 epi0 rrrrrrrr bit function epi7 endpoint interrupt 7 request flag if epi7 is set, an endpoint interrupt 7 request is pending. epi6 endpoint interrupt 6 request flag if epi6 is set, an endpoint interrupt 6 request is pending. epi5 endpoint interrupt 5 request flag if epi5 is set, an endpoint interrupt 5 request is pending. epi4 endpoint interrupt 4 request flag if epi4 is set, an endpoint interrupt 4 request is pending. epi3 endpoint interrupt 3 request flag if epi3 is set, an endpoint interrupt 3 request is pending. epi2 endpoint interrupt 2 request flag if epi2 is set, an endpoint interrupt 2 request is pending. epi1 endpoint interrupt 1 request flag if epi1 is set, an endpoint interrupt 1 request is pending. epi0 endpoint interrupt 0 request flag if epi0 is set, an endpoint interrupt 0 request is pending. psb 2154 interrupt system data sheet 304 2001-01-24 6.1.1.7 ciari - configuration request interrupt register the configuration, interface & alternate setting interrupt register (ciari) sends an interrupt to the c whenever the host programs multiple device configurations or interfaces. resetvalue:00 h address: d7 h the interrupt contained in the ciari register can be masked in the ciarie register. note: this interrupt is an additional usb device interrupt and shares the vector address 002b h . 76543210 0000000drvi rrrrrrrr bit function drvi device request value interrupt bit drvi is set each time the host sends a device request that contains one or more of the following: configuration value interface, alternate setting this flag can only be cleared by writing a 0 to the bit. writing a 1 to the bit will be ignored. the interrupt has to be enabled by bit drvie before being used. psb 2154 interrupt system data sheet 305 2001-01-24 6.1.1.8 ista - isdn status register the ista register is described in detail with the isdn registers in chapter 5.8 . resetvalue:01 h address: f860 h the interrupts contained in the ista register can individually be masked in the mask register. for all interrupts in the isdn status register ista, the following logical states are applied: 0: interrupt is not active 1: interrupt is active note: a read of the ista register clears none of the interrupts. they are only cleared by reading the corresponding status register. 76543210 ica icb st cic aux tran mos icd rrrrrrrr bit function ica hdlc interrupt from b-channel a icb hdlc interrupt from b-channel b st synchronous transfe r to enable the microcontroller to lock on to the iom timing for synchronous transfers, the source can be read from the sti register cic ci channel change a change on c/i channel 0 or c/i channel 1 has been recognised. the actual value can be read from cir0 or cir1 aux auxiliary interrupt indicates watchdog timer overflow, timer 1 or timer 2 time-out or an external interrupt int1 / int2 , the source can be read from the auxiliary interrupt register auxi tran transceiver interrupt indicates an interrupt from the transceiver interrupt status register istatr mos monitor status indicates a change in the monitor status register (mosr) icd hdlc interrupt from d-channel psb 2154 interrupt system data sheet 306 2001-01-24 6.1.2 interrupt enable registers each interrupt can be individually enabled or disabled by setting or clearing the corresponding bit in the global interrupt enable registers ien0, ien1 and ien2, the usb specific dier, epien and epbcn registers or the isdn specific enable registers. register ien0 also contains the global disable bit (eal), which can be cleared to disable all interrupts at once. the usb and isdn interrupt sources have further enable bits for individual interrupt control. the ien0 register contains the general enable/disable flags of the external interrupt 0, the timer interrupts and 2 other interrupts. the 2 usb interrupts are enabled/disabled by bits in the ien0/1 registers. the 8 isdn interrupts are enabled/disabled by bits in the ien1/2 registers. after reset, the enable bits of ien0, ien1 and ien2 are set to 0, i.e. the corresponding interrupts are disabled. 6.1.2.1 ien0 - interrupt enable register 0 resetvalue:00 h address: a8 h note: res. = bit is reserved and must not be changed. 76543210 eal 0 ex5 es et1 res. et0 ex0 rw r rwrwrwrwrwrw bit function eal enable all interrupts when set to 0, all interrupts are disabled. when set to 1, interrupts are individually enabled/disabled according to their respective bit selection. ex5 enable external interrupt 5 - udci (usb device interrupt) es enable spi eeprom control interrupt - epcint (eeprom control int) et1 enable timer 1 overflow interrupt et0 enable timer 0 overflow interrupt ex0 enable external interrupt 0 - int0 the int0 interrupt can only be disabled in operational and idle mode. in suspend mode this interrupt is directly routed to the nmi service routine, i.e. bit ex0 is don ? t care in suspend mode. psb 2154 interrupt system data sheet 307 2001-01-24 6.1.2.2 ien1- interrupt enable register 1 resetvalue:00 h address: a9 h 6.1.2.3 ien2 - interrupt enable register 2 resetvalue:00 h address: aa h note: res. = bit is reserved and must not be changed. 76543210 0 0 ex11 ex10 ex9 ex8 ex7 ex6 r r rw rw rw rw rw rw bit function ex11 enable external interrupt 11 -tran (transceiver) ex10 enable external interrupt 10 -mos (monitor status) ex9 enable external interrupt 9 -st (synchronous transfer) ex8 enable external interrupt 8 -icd (hdlc d-channel) ex7 enable external interrupt 7 -ica (hdlc b-channel a) ex6 enable external interrupt 6 -epi (usb endpoint interrupt) 76543210 0 0 res. res. res. ex14 ex13 ex12 rrrrrrwrwrw bit function ex14 enable external interrupt 14-aux (auxiliary functions) ex13 enable external interrupt 13 -icb (hdlc b-channel b) ex12 enable external interrupt 12 -cic (c/i code change) psb 2154 interrupt system data sheet 308 2001-01-24 6.1.2.4 dier - usb device interrupt enable register the device interrupt enable register dier contains the enable bits for the different usb device interrupts. a device interrupt can only be generated if ien0.ex5 and eal are set too. resetvalue:00 h address: c3 h for accessing dier, the sfr epsel must be 80 h . the interrupts contained in the dirr register can individually be masked in the dier register. 76543210 se0ie daie ddie sbie seie stie suie sofie rw rw rw rw rw rw rw rw bit function se0ie single ended zero interrupt enable daie device attached interrupt enable ddie device detached interrupt enable sbie suspend begin interrupt enable seie suspend change interrupt enable stie status interrupt enable suie setup interrupt enable sofie start of frame interrupt enable psb 2154 interrupt system data sheet 309 2001-01-24 6.1.2.5 epien - usb endpoint interrupt enable register resetvalue:00 h address: c3 h the endpoint interrupt enable registers contain the endpoint specific interrupt enable bits. with these bits, the endpoint specific interrupts can be individually enabled or disabled. in addition to a bit in an epien register, the global interrupt bit epin in gepir for endpoint n and the general endpoint interrupt bit ien1.ex6 and the general interrupt enable bit ien0.eal must be set for the interrupt to become active. for accessing epien, the sfr epsel must be 0n h . 76543210 aien naien rleien 0 dnrien nodien eodien sodien rwrwrw r rwrwrwrw bit function aien acknowledge interrupt enable bit aien enables the generation of an endpoint specific acknowledge interrupt when bit ackn in register epirn is set. naien not acknowledged interrupt enable bit naien enables the generation of an endpoint specific not acknowledged interrupt when bit nackn in register epirn is set. rleien read length error interrupt enable bit rleien enables the generation of an endpoint specific read length error interrupt when bit rlen in register epirn is set. dnrien data not ready interrupt enable bit dnrien enables the generation of an endpoint specific data not ready interrupt when bit dnrn in register epirn is set. nodien no data interrupt enable bit nodien enables the generation of an endpoint specific no data interrupt when bit nodn in register epirn is set. eodien end of data interrupt enable bit eodien enables the generation of an endpoint specific end of data interrupt when bit eodn in register epirn is set. sodien start of data interrupt enable bit sodien enables the generation of an endpoint specific start of data interrupt when bit sodn in register epirn is set. psb 2154 interrupt system data sheet 310 2001-01-24 6.1.2.6 epbcn - endpoint n buffer control register (n=0-7) resetvalue:00 h address: c1 h for accessing epbcn registers, the sfr epsel must be 0n h . note: the shaded bits are not used for interrupt control. 6.1.2.7 ciarie - configuration request interrupt enable resetvalue:00 h address: d8 h 76543210 stalln 0 0gepien sofden incen 0 dbmn rw r r rw rw rw r rw bit function gepien global endpoint interrupt enable bit gepien enables or disables the generation of the global endpoint interrupt for endpoint n based on the endpoint specific interrupt request bits in register epirn. gepien is used to enable/disable a specific endpoint interrupt, whereas ien1.ex6 enables/disables all endpoint interrupts irrespective of gepien. 76543210 0000000drvie rrrrrrrrw bit function drvie device request value interrupt enable when 1, this bit enables the device request value interrupt. psb 2154 interrupt system data sheet 311 2001-01-24 6.1.2.8 ista_init - isdn interrupt status register initialize resetvalue:ff h address: f860 h in order to enable isdn interrupt generation to the microcontroller, the ista_init register must be programmed to 00 h after reset. after that this register should not be changed any more. enabling and disabling of isdn interrupts (ista register) should be done in the interrupt enable registers ien1 and ien2. 76543210 rw rw rw rw rw rw rw rw psb 2154 interrupt system data sheet 312 2001-01-24 6.1.3 interrupt priority for the purposes of assigning priority, the 14 interrupt sources are divided into groups determined by their bit position in the interrupt enable registers and their respective requests are scanned in the order shown below. in the standard configuration, each interrupt group may be individually assigned to one of four priority levels by writing to the ip0 and ip1 interrupt priority registers at the corresponding bit position. an interrupt service routine may only be interrupted by an interrupt of higher priority, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. an interrupt can not be interrupted by another interrupt of the same or a lower priority level. if two interrupts of the same priority level occur simultaneously, the order in which the interrupts are serviced is determined by the scan order shown above, i.e. if two groups are programmed to the same priority level, the priority of these two groups within this level is as shown in table 29 . table 29 interrupt priority order interrupt group 0 (bit 0) external interrupt 0 ext int 6 (usb endpoint) ext int 12 (cic) 1 (bit 1) timer 0 overflow ext int 7 (ica) ext int 13 (icb) 2 (bit 2) not used ext int 8 (icd) ext int 14 (aux) 3 (bit 3) timer 1 overflow ext int 9 (st) 4 (bit 4) es (eeprom control) ext int 10 (mos) 5 (bit 5) ext int 5 (usb device) ext int 11 (tran) high low high low psb 2154 interrupt system data sheet 313 2001-01-24 6.1.3.1 ip0 / ip1 - endpoint priority registers resetvalue:00 h address: b8 h resetvalue:00 h address: ac h note: x = interrupt group as shown in table 29 . 76543210 ip0 0 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r r rw rw rw rw rw rw 76543210 ip1 0 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r r rw rw rw rw rw rw bit function ip1.0 - ip0.0 (group 0) ip1.1 - ip0.1 (group 1) ip1.2 - ip0.2 (group 2) ip1.3 - ip0.3 (group 3) ip1.4 - ip0.4 (group 4) ip1.5 - ip0.5 (group 5) interrupt group priority level set as follows: 00 = group x set to priority level 0 (lowest) 01 = group x set to priority level 1 10 = group x set to priority level 2 11 = group x set to priority level 3 (highest) a pair of bits from the ip0 and ip1 registers is used for one group to select its priority. psb 2154 interrupt system data sheet 314 2001-01-24 6.2 interrupt handling the interrupt flags are sampled at s5p2 in each machine cycle. the samples flags are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate a long call (lcall) to the appropriate service routine. in some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this has to be done by the user ? s software. if any interrupt flag is active but not being responded to, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not serviced is not remembered. when an interrupt is serviced, a long call instruction is executed to one of the locations listed in the following table: note: the non maskable interrupt (nmi) input to the c800 core is activated by a wakeup from suspend mode. the c then branches to address 007b h . table 30 interrupt vectors interrupt source interrupt enable vector address interrupt request flag register bit (hex) external interrupt 0 ien0 ex0 0003 tcon.ie0 timer 0 overflow ien0 et0 000b tcon.tf0 0013 (not used) timer 1 overflow ien0 et1 001b tcon.tf1 spi interface ien0 es 0023 eepint.epcint usb device interrupt ien0 ex5 002b dirr, ciari, dsir usb endpoint interrupt ien1 ex6 0033 gepir isdn b-channel a ien1 ex7 003b ista.ica isdn d-channel ien1 ex8 0043 ista.icd isdn synchronous transfer ien1 ex9 004b ista.st isdn monitor channel ien1 ex10 0053 ista.mos isdn transceiver interrupt ien1 ex11 005b ista.tran isdn c/i channel interrupt ien2 ex12 0063 ista.cic isdn b-channel b ien2 ex13 006b ista.icb auxiliary interface interrupt ien2 ex14 0083 ista.aux 007b non maskable interrupt psb 2154 interrupt system data sheet 315 2001-01-24 the external interrupt from pin int0 which is indicated in tcon.ie0 can only be disabled via ien0.ex0 in operational and idle mode, but in suspend mode ex0 has no effect. the vector address shown in the table above is only valid for operational and idle mode, in suspend mode the int0 interrupt is directly routed to the nmi. 6.3 wakeup from suspend in suspend mode certain events can wakeup the device which are usb resume (activity is detected on the bus) external interrupt from pin int0 , int1 , int2 and eaw level detect on s interface (incoming call is detected) c/i-code change is detected before going into suspend mode the wakeup sources are individually enabled and disabled in the wakeup control register (wcon) and in some specific mask registers ( figure 116 ). figure 116 wakeup sources in suspend mode icd mos tran aux cic st icb ica icd mos tran aux cic st icb ica sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 sti10 sti11 sti20 sti21 stov10 stov11 stov20 stov21 istab sti ack10 ack11 ack20 ack21 asti xdu xpr rfo rpf rme xdu xpr rfo rpf rme xdu xpr rfo rpf rme xdu xpr rfo rpf rme maskb msti ci1e cic1 cic0 cir0 cix1 xdu xmr xpr rfo rpf rme maskd xdu xmr xpr rfo rpf rme istad mie mre mab mda mer mdr sqw sqc ric ld masktr istatr sqw sqc ric ld ien1 ien2 ista 2154_88 interrupts istab maskb b-channel a b-channel b mocr mosr int1 int2 tin1 tin2 wov auxm auxi int1 int2 tin1 tin2 wov eaw eaw d-channel wptr wpci wpio wpus wcon ewpd wcon tcon1.ie0 int0 (external interrupt int0) wakeup from suspend in suspend mode only dirr.sei (usb resume on the bus) nmi psb 2154 interrupt system data sheet 316 2001-01-24 the wcon.ewpd bit (external wakeup from power down enable) is used to enable/ disable all wakeup sources in general. another four bits in the same register are used to individually control four groups of wakeup sources ( table 31 ). for all wakeup events from the isdn block (except cic0) the corresponding mask bit can be used to disable the event as wakeup source individually. the vector address of the interrupt source in normal operation mode (see table 30 ) is not valid in suspend mode and the corresponding interrupt status bit is not set when a wakeup event occurs. instead, in suspend mode the wakeup source is directly routed to the nmi with the corresponding interrupt vector address 007b h . this means that the actual wakeup source cannot be determined if more than one wakeup source was enabled. note: it should be noted that the control function "level detect discard" (trconf0.ldd) should not be used to disable the wakeup function from the s interface in suspend mode. instead, the wcon.wptr should be used to control this wakeup source. table 31 enabling / disabling of wakeup sources enable / disable via wakeup source description wcon-register mask- register ewpd wpus dirr.sei usb resume on the bus wpio tcon.ie0 external interrupt from int0 wpci auxm.int1 auxi.int1 external interrupt from int1 auxm.int2 auxi.int2 external interrupt from int2 auxm.eaw auxi.eaw external interrupt from eaw cir0.cic0 c/i0-code change cix1.ci1e cir0.cic1 c/i1-code change wptr masktr.ld istatr.ld level detect on s interface psb 2154 interrupt system data sheet 317 2001-01-24 suspend mode with disabled remote wakeup special care should be taken if the device is going into suspend mode while the remote wakeup capability is disabled (e.g. the host previously sent a set_feature command with ? remote wakeup disabled ? ). before going to suspend mode all wakeup sources - except usb resume on the bus (dirr.sei) - should be disabled via the wcon-register and their respective mask registers. additionally, the s-transceiver should be switched off completely (tr_conf0.dis_tr = 1) and the reset source selection should be disabled (mode1.rss2,1 = 00). note: to avoid floating inputs at fsc and dcl, pull up resistors should be provided as both clock signals become input when the transceiver is switched off. psb 2154 firmware data sheet 318 2001-01-24 7firmware the firmware that is provided with the siuc-x implements various functions that allow fast and efficient system design. it consists of an embedded universal boot loader contained in rom and downloadable operational firmware. 7.1 firmware operation modes the siuc-x provides the ability to download microcontroller code into internal or external memory. this allows for flexible firmware upgrades and reduces the risk of changing standards (e.g. usb or isdn specifications). table 32 shows which boot modes are selected by pin strapping. a boot loader is contained in rom and after reset the c reads the bmod1-0 pins (register hcon) to perform one of the described operations. pin ea determines whether the firmware execution should start from internal rom (performing the download) or external memory (e.g. eprom). note: x = don ? t care table 32 boot mode selection state of pin ea selection by pinstrapping mode description bmod1 bmod0 0xx eprom mode operation is started from non-volatile external memory, i.e. after reset the c starts execution from external memory and the bootloader in internal rom is ignored. 100 download mode the firmware is downloaded from the host via usb into the internal (and optionally: external) ram of the siuc- x. this is controlled by the onchip bootloader contained in rom. the download firmware can either be the ready to use firmware provided by infineon technologies, or it can be propietary customer firmware. 1 0 1 reserved for further use. 110 111 test mode this mode is reserved for manufacturing test. psb 2154 firmware data sheet 319 2001-01-24 7.2 boot loader firmware the operations performed after reset are shown in figure 117 . figure 117 bootmode procedure after a power on reset, the c either executes firmware from external memory (ea =0, eprom mode) or the bootloader from internal rom (ea =1). in eprom mode the boot loader in internal rom is ignored and the following procedure as well as figure 117 is not applicable. the boot loader executed in firmware download mode is located in rom. which boot mode is selected? (hcon.bmod) reset execute firmware from external memory execute firmware in rom (bootloader) eeprom mode download mode loading from eeprom ? (eepsl.eld=1) read eeprom contents and initialize configuration data use default settings in rom yes no export dfu descriptor transfer system information in string descriptor to host system information: mmod, bmod1/2, svn1/0, ... firmware download host performs usb reset export cdc descriptor downloaded firmware contains usb configuration data (vendorid, ...) for normal operation mode. from this point onwards the downloaded firmware performs all operations on the siuc. from this point onwards the bootloader performs all operations on the siuc. continue with normal operation 2154_32 initialization of the siuc psb 2154 firmware data sheet 320 2001-01-24 pin eld (a multiplexed function of pin aux3) which is read via register eepsl.eld indicates whether the c should load usb configuration data (vendor id, device id,... ) from external eeprom or whether default settings in internal rom should be used. the boot loader initializes the cpu and the usb core with the dfu (device firmware upgrade) configuration and - upon host request - exports a dfu descriptor to the host, indicating that this device requires a firmware download. this usb configuration uses only the default endpoint (ep0) with the buffer size set to 64 bytes. after initialization, the boot loader waits for commands (some of them are vendor specific) to get: the download firmware including a header with information about it (size, vendor id and product id or their sources, ...) note: as the siuc-x supports an spi interface to an eeprom, the connected eeprom can be the source for a vendor specific encryption key. the ids are always downloaded. commands to program the eeprom a command, which aborts the download on request from the host a command, which finishes the download and says "i will send you a reset within the next few milliseconds. you have to restart and execute the operational firmware". after the command the device waits for a reset on the usb bus. then it activates the firmware reset (set the c software reset bit syscon2.stat1 and execute the operational firmware). the download of operational firmware and usb configuration data is done according to the usb device class spec dfu (d evice f irmware u pgrade). the validity of the download is signaled to the host on a get_status request (vendor specific). the bootloader is able to do another download if required. this switching between download and operational firmware is controlled by bit syscon2.stat2. the switching from bootloader to the operational firmware is only done when triggered by software; it is also possible to switch back to the bootloader for a run-time update. after this download a usb reset is executed on the siuc and the c executes the downloaded firmware in ram. the firmware provided together with the siuc will then export a cdc descriptor (usb c ommunication d evices c lass) and identify itself as an isdn communications device. from this point on normal operation according to cdc is done. psb 2154 firmware data sheet 321 2001-01-24 system identification the siuc provides the possibility to identify different system configurations of the device hardware to the host. this enables the host to select the appropriate download firmware for a specific hardware configuration. three strap pins are latched during reset and can be read from the hardware configuration register hcon (a3 h ): mmod - is used to differentiate between shared memory ( ? 0 ? ) and separate memories ( ? 1 ? ) on the external memory interface. this pin has no effect on the hw functions of the siuc, but is only used as indication for the c. svn0, svn1 - two pins on the auxiliary interface are used as strap pins during reset to set the corresponding svn0,1 bits in the hcon register. in addition to that another 3 bits (svn4-2) are available in the hcon register which can be overwritten by a value from a connected eeprom. if no eeprom is used, svn5-0 is not overwritten by the c (i.e. svn4-2 remains 000 b and svn1-0 contain the pin strap values). the svnx bits have no influence on the hw functions of the device but they can be used as an identification number for different hw configurations. bmod0, bmod1 - the bootmode pins are used to select the firmware download mode (see chapter 7.1 ) which can be read from the hcon register. the hcon register is transferred to the host by means of a string descriptor. this allows the host software to identify the system and load the appropriate firmware and driver software. this identification requires no eeprom (single chip application). with external eeprom connected another 3 bits (svn4-2) can be loaded, i.e. a 5-bit value for system version number is available and can be used by host software for identification. psb 2154 firmware data sheet 322 2001-01-24 7.3 memory configurations embedded in the siuc-x are several memories that become active depending on the mmod and bmod strapping and the usb configuration. 4 kbyte boot loader rom 16 kbyte mixed program / data ram that can be configured using the psiz, dsiz registers (e.g. 6 kbyte program and 10 kbyte data) external memory extension for up to 64 kbyte program and 62 kbyte data memory reduced extension with shared program and data memory, e.g. one 32kx8 device for program and data memory extension (see figure 118 ). figure 118 shared and separate external memory expansion the physical interface and the associated signals are described in chapter 3.3 . the following chapters describe examples for different memory configurations: firmware download mode the bootloader in internal rom performs firmware download via usb into internal/ external memory. firmware execution in (internal) ram in single chip mode normal operation mode with no memory extension. firmware execution in (internal/external) ram with memory extension - shared memory extension (program and data in one memory device) - separate memory extension (program and data in separate memory devices) firmware execution in eprom after reset the c starts execution from external memory. a.0-7 p2.0-7 a0-7 a8-15 p0.0-7 d0-7 p3.2 / wr p3.3 / rd psen wr oe cs external memory (prog and data) shared external memory, mmod=0 (program and data in one single memory) a0-7 a8-15 d0-7 wr oe cs separate external memory, mmod=1 (program and data in separate memories) external memory (data) a0-7 a8-15 d0-7 external memory (program) 2154_69 a.0-7 p2.0-7 p0.0-7 ale / cs p3.3 / rd psen p3.4 / pwr wr oe cs p3.2 / wr ale / cs p3.4 / pwr psb 2154 firmware data sheet 323 2001-01-24 7.3.1 firmware download mode the memory map used for the download mode is shown in figure 119 . the boot loader is present inside the 4 kbyte program rom which is not visible during normal operation mode. firmware is downloaded to the 16 kbyte internal ram and optionally to up to 48 kbyte external memory space. after the download is finished the external memory can be used as program or data memory. the external memory address 0000h is mapped to the internal address 4000h. for a 64 kbyte sram the upper 16 kbyte chunk is used as data memory during normal operation mode with shared memory (see chapter 7.3.3.1 ). this 16 kbyte space is unused with separate memories ( chapter 7.3.3.2 ). figure 119 memory map for firmware download download mode "program space" "internal data space" 2154_35.vsd on chip data --- internal ram 1 0000 h 3fff h 16 kbyte "external data space" off chip data --- external ram 1 4000 h ffff h 48 kbyte on chip program --- rom download fw 0000 h 0fff h 4kbyte internal ram 80 h ff h special function registers 80 h ff h internal ram 00 h 7f h mapping to external memory address space ffff h c000 h bfff h 0000 h firmware download to internal memory (16 kbyte). extension of download space up to 64k is possible by connecting external memory. no access in download mode external memory psb 2154 firmware data sheet 324 2001-01-24 7.3.2 firmware execution in ram - single chip mode figure 120 shows the memory map used during execution of the downloaded firmware (normal operation mode). during execution the bootloader program rom is invisible and the downloaded firmware takes over. a switch from download mode to execution mode takes place after the download is finished (syscon2.stat2). in this example, the 16 kbyte internal ram has been configured to work as 6 kbyte program ( ram1 ) and 10 kbyte data ( ram2 ). the size of internal program memory is programmed in psiz, the remaining space is used as data memory (dsiz) which must be programmed before giving a software reset to the c and switching back the data space to program memory space (normal execution mode). the onchip data memory (dsiz) is always located right below the isdn registers (below address f800h). figure 120 firmware execution in ram - single chip mode ram-execution mode in single-chip application "program space" "internal data space" 2154_36.vsd off chip data --- external ram 2 (not used) 0000 h cfff h 52 kbyte "external data space" isdn interface f800 h ffff h 2kbyte on chip data --- internal ram d000 h f7ff h 10 kbyte (dsiz) internal ram 80 h ff h special function registers 80 h ff h internal ram 00 h 7f h off chip program --- external ram 1 (not used) 1800 h ffff h 58 kbyte on chip program --- internal ram 0000 h 17ff h 6kbyte (psiz) example for partitioning of on chip ram: - onchipprogramram: 6kbyte(psiz) - onchipdataram: 10kbyte(dsiz) psb 2154 firmware data sheet 325 2001-01-24 7.3.3 firmware execution in ram - memory extension in order to have a contiguous address space between onchip and offchip program memory (at program address 4000h) it is required to set the registers psiz (program size) to 16 kbyte and dsiz (data size) to 0 kbyte. a general description of the address mapping between internal and external address space can be found in chapter 3.2.1 . 7.3.3.1 extension with shared memory shared memory extension (mmod=0) means that program and data is located in the same physical memory ( figure 121 ). during download the code is written to the external memory using the wr signal (pwr is not used) and verification (read back) is done using the rd strobe. during normal operation data access is done by rd /wr strobes, while opcode fetches are done using the psen signal. however, the read strobes for program and data can internally be gated together to avoid the necessity of external logic. if syscon1.stat0 is set to "1" the combined rd and psen signal is available at the rd pin. figure 121 shared memory expansion a.0-7 p2.0-7 a0-7 a8-15 p0.0-7 d0-7 p3.2 / wr p3.3 / rd psen wr oe cs external memory (prog and data) shared external memory, mmod=0 (program and data in one single memory) ale / cs p3.4 / pwr syscon1.stat0=1 2154_69 "psen" "rd" "xxx" = internal signal psb 2154 firmware data sheet 326 2001-01-24 below are two examples for extension with a single 32k or 64k memory for both program and data. figure 122 shows the example with a 32kx8 ram that can flexibly used for program and data space. the partitioning into external program and data space can be done in any way as the access is perfomed with the same bus and control signals. only the user needs to take care to prevent an overlap of program and data spaces. figure 122 firmware execution in ram - example with one 32k memory figure 123 shows an example with a 64kx8 ram that can flexibly used for program and data space. here the full 64k range for program is used. the upper 16k junk of the external memory is always mapped to address 0000h of data space. ram-execution mode with memory extension (1) "program space" "internal data space" 2154_36.vsd not used c000 h f7ff h 14 kbyte "external data space" isdn interface f800 h ffff h 2kbyte internal ram 80 h ff h special function registers 80 h ff h internal ram 00 h 7f h not used --- no memory 8800 h ffff h 30 kbyte on chip program --- internal ram 0000 h 3fff h 16 kbyte (psiz) example for external memory extension (32k x 8): - onchipprogramram: 16kbyte(psiz) - onchipdataram: 0kbyte(dsiz) -offchipprogramram: 18kbyte - offcipdataram: 14kbyte off chip data --- external ram 8800 h bfff h 14 kbyte off chip program --- external ram 4000 h 87ff h 18 kbyte not used --- no memory 0000 h 87ff h 34 kbyte 47ff h -prog- 0000 h 7fff h -data- 4800 h external memory 32kx8 14 kbyte 18 kbyte psb 2154 firmware data sheet 327 2001-01-24 figure 123 firmware execution in ram - example with one 64k memory ram-execution mode with memory extension (2) "program space" "internal data space" 2154_36.vsd not used 4000 h f7ff h 46 kbyte "external data space" isdn interface f800 h ffff h 2kbyte internal ram 80 h ff h special function registers 80 h ff h internal ram 00 h 7f h on chip program --- internal ram 0000 h 3fff h 16 kbyte (psiz) example for external memory extension (64k x 8): - onchipprogramram: 16kbyte(psiz) - onchipdataram: 0kbyte(dsiz) -offchipprogramram: 48kbyte - offcipdataram: 16kbyte off chip program --- external ram 1 4000 h ffff h 48 kbyte bfff h -prog- 0000 h ffff h -data- c000 h external memory 64kx8 16 kbyte 48 kbyte off chip data --- external ram 2 0000 h 3fff h 16 kbyte psb 2154 firmware data sheet 328 2001-01-24 7.3.3.2 extension with separate memories figure 124 shows an example for extension with a 64kx8 program ram and 32kx8 data ram. in this case the external rams are accessed by using different read strobe signals (rd /psen ). in this way the total address space of 64k can be used for program and up to 62k for data memory (2k used for isdn registers). the 16k overlap of the 64k program memory is not used in this configuration. with a 64k data memory the upper 2k cannot be used. figure 124 firmware execution in ram - example with separate memories ram-execution mode with memory extension (3) "program space" "internal data space" 2154_36.vsd not used c000 h f7ff h 14 kbyte "external data space" isdn interface f800 h ffff h 2kbyte internal ram 80 h ff h special function registers 80 h ff h internal ram 00 h 7f h on chip program --- internal ram 0000 h 3fff h 16 kbyte (psiz) example for external program memory (64k x 8) and data memory extension (32k x 8): - on chip program ram: 16 kbyte (psiz) - onchipdataram: 0kbyte(dsiz) - off chip program ram: 48 kbyte - offcipdataram: 32kbyte off chip program --- external ram 1 4000 h ffff h 48 kbyte bfff h -prog- 0000 h ffff h - not used - c000 h external prog memory 64kx8 16 kbyte 48 kbyte off chip data --- external ram 2 4000 h bfff h 32 kbyte 7fff h -data- 0000 h external data memory 32kx8 32 kbyte not used 0000 h 3fff h 16 kbyte psb 2154 firmware data sheet 329 2001-01-24 7.3.4 firmware execution in external eprom figure 125 shows the memory configuration used to execute firmware from offchip eprom (pin ea =0). in this case no download is necessary, neither are the contents of psiz and dsiz valid. the internal 16 kbyte ram is always used for data memory. the remaining 46 kbyte data space can be extended by external ram if required. any access to the internal 16 kbyte data ram and to the isdn registers will not activate the external memory interface, i.e. only 46 kbyte of external data space can be used. figure 125 memory map for firmware execution in external eprom eprom-execution mode "program space" "internal data space" 2154_37.vsd off chip data --- external ram 0000 h b7ff h 46 kbyte "external data space" isdn interface f800 h ffff h 2kbyte on chip data --- internal ram b800 h f7ff h 16 kbyte off chip program --- external eprom 0000 h ffff h 64 kbyte internal ram 80 h ff h special function registers 80 h ff h internal ram 00 h 7f h psb 2154 firmware data sheet 330 2001-01-24 7.4 usb models 7.4.1 general usb model in siuc figure 127 gives a general view on the usb models that can be built with the siuc and its usb device core (udc). it provides 4 interfaces in addition to the default interface 0, 2 alternate settings for each interface and 7 configurable endpoints besides the default endpoint 0. the assignment of endpoints to an interface is just depending on the application, so the device class supported by the siuc is determined by the firmware running on it. the following two chapters already show specific implementations of specific device classes which are used for isdn data access application. however, the siuc allows any class specific implementation within its usb resources of interfaces and endpoints. it should be noted that the udc counts the functional interfaces 1 - 4 with the interface numbers ifc = 0 - 3. however the usb specifications considers the default endpoint 0 as a separate interface (interface 0). figure 126 general usb model interface 0 interface 1 as1 as0 interface 2 as1 as0 interface 3 as1 as0 interface 4 as1 as0 configuration 1 2154_34 ep2 ep1 ep4 ep3 ep6 ep5 ep7 ep0 pool of 7 configurable endpoints assignment of endpoints to interfaces is application specific. ifc 0 ifc 1 ifc 2 ifc 3 psb 2154 firmware data sheet 331 2001-01-24 7.4.2 usb model in download mode (dfu) the siuc-x supports download of c code via usb into internal and external memory. the boot loader program which resides in internal prom is operating compliant to the usb class specification for device firmware upgrade (dfu). the usb configuration on the siuc-x used in this mode is shown in figure 127 . only the default endpoint (ep0) is used for bulk data transfer with a buffer size of 2x64-byte. figure 127 usb configuration in dfu mode 7.4.3 usb model in operational mode (cdc) the firmware that is provided with the siuc-x provides a logical link between the isdn part of the device and the usb interface, and performs the access to the isdn specific registers for transfer of control/status information and b- and d-channel data ( figure 128 ). figure 128 siuc-x firmware operation the microcontroller provides the access to the fifos and hdlc controllers and exchanges this data between the host and the isdn registers in a specific way which is specified in the usb communication device class specification (cdc) version 1.1. in configuration 1 interface 0 dfu class ep 0 control 2154_34 usb interface c memory isdn functions s interface usb usb host siuc isdn basic rate access 2154_34 psb 2154 firmware data sheet 332 2001-01-24 other words, the host does not need to initiate the c to read and write data from the fifos, this is done automatically by the provided firmware. the mechanism how and in which format data is exchanged is described in the usb cdc spec. communication devices present data to the host in a form defined by another class such as audio, data or human interface. to allow the appropriate class driver to manage that data, the host is presented with an interface, which obeys the specification of that class. the interface that is required may change according to events that are initiated by the user or the network during a communication session, e.g. the transition from a data only call to a data and voice call. the functional characteristics include: device organisation ? 7 configurable endpoints + default endpoint (ep0) ? construction of interfaces from endpoints (4 interfaces + default interface 0) ? construction of configurations from interfaces and alternate settings (siuc-x firmware supports one configuration at a time) device operation a communication device has three basic responsibilities: ? device management ? call management ? data transmission the device uses a communication class interface to perform device management and optionally, call management (see figure 129 ) via default endpoint 0 which is a bidirectional endpoint (control transfer). device management refers to requests and notifications that control and configure the operational state of the device, as well as notify the host of events occurring on the device. call management refers to setting up and tearing down of calls. this same process also controls the operational parameters of the call. data transmission is accomplished using data class interfaces for d-channel data and for each of the two b-channels (two unidirectional endpoints each). another interface may be used to provide synchronisation data to the host for b-channel data transfer. basically, all device endpoints (ep1-ep7) beside ep0 can support all four usb transfer modes. as data class interface in this firmware model they are used as isochronous or bulk endpoints. all data class interfaces support two alternate settings, one for operational state (as1) and a default alternate setting (as0) which means "no operation". this releases bandwidth in idle mode and conforms to the bandwidth managment requirements on usb. psb 2154 firmware data sheet 333 2001-01-24 figure 129 usb configuration in cdc mode data buffer size (cdc) within the usb module the data buffer sizes are programmable for each endpoint. the siuc-x firmware supporting cdc uses the following data buffer sizes for each endpoint: ep0: 2x8-byte (control) ep1: 2x8-byte (d-channel) ep2: 2x8-byte (d-channel) ep3: 2x16-byte (b1-channel) ep4: 2x16-byte (b1-channel) ep5: 2x16-byte (b2-channel) ep6: 2x16-byte (b2-channel) ep7: 2x8-byte (not used here) the endpoint 7 (ep7) is not used in the configuration supported by the siuc firmware from infineon technologies. however, it may be used for different implementations than this (e.g. b-channel sync in cdc spec). management b-channel 2 interface 0 comm class ep0 interface 1 data class as1 as0 ep2 ep1 interface 2 data class as1 as0 ep4 ep3 interface 3 data class as1 as0 ep6 ep5 configuration 1 (in) (out) (in) (out) (in) (out) d-channel b-channel 1 2154_34 psb 2154 firmware data sheet 334 2001-01-24 7.4.4 usb configuration data during the usb configuration procedures the siuc identifies itself by means of several id values and set of strings. if no eeprom is connected the values are loaded with default settings from internal rom. an external eeprom is used to initialize all values after power on reset with customer specific values. the siuc uses two operational modes where it identifies itself with different sets of descriptors: dfu (device firmware upgrade) class - descriptor this descriptor is exported by the bootloader firmware located in rom which performs the download of the functional firmware into the siuc ? s memory. if no eeprom is connected, the configuration parameters are set by default values in rom. cdc (communication device class) - descriptor after the firmware download is finished and a usb reset is generated by the host, the siuc exports the cdc descriptor, i.e. the siuc identifies itself as an isdn communications device compliant to the usb cdc v1.1 spec. as the configuration parameters are loaded together with the downloaded firmware, a file containing these configuration data is provided by the system manufacturer which are downloaded together with the firmware file. if no file is provided default settings are used. table 33 siuc configuration data for usb descriptors value no eeprom connected eeprom connected idvendor dfu:0x058b ("infineon technologies") cdc:downloaded by fw (default: 0x058b) dfu: value from eeprom cdc downloaded by fw (default: 0x058b) idproduct dfu:0x8002 cdc:downloaded by fw (default: 0x0002) dfu: value from eeprom cdc downloaded by fw (default: 0x0002) bcddevice dfu:0x0101 (version 1.1) cdc: downloaded by fw (default: 0x0101) dfu: value from eeprom cdc downloaded by fw (default: 0x0101) bcdusb dfu:0x0101 ("usb v1.1") cdc:downloaded by fw (default: 0x0101) dfu: value from eeprom cdc downloaded by fw (default: 0x0101) psb 2154 firmware data sheet 335 2001-01-24 bdeviceclass dfu:0xfeh ("application specific class") cdc:downloaded by fw (default: 0x02, i.e. usb cdc) dfu: value from eeprom cdc downloaded by fw (default: 0x02, i.e. usb cdc) bdevicesubclas s dfu:0x01h ("dfu") cdc:downloaded by fw (default: 0x04, i.e. multichannel control model) dfu: value from eeprom cdc downloaded by fw (default: 0x04, i.e. multichannel control model) bdeviceprotocol dfu:0x00 ("no specific protocol") cdc:downloaded by fw (default: 0xff; vendor specific) dfu: value from eeprom cdc downloaded by fw (default: 0xff; vendor specific) bmattributes dfu:0x80 (not self-powered, no rem. wakeup) cdc:downloaded by fw (default: 0x80, not self-powered, no rem. wakeup) dfu: value from eeprom cdc downloaded by fw (default: 0x80, not self-powered, no rem. wakeup) maxpower dfu:0x32 (100 ma, see note) cdc: downloaded by fw (default: 0x32) dfu: value from eeprom cdc downloaded by fw (default: 0x32) strmanufacturer dfu:"infineon technologies" cdc: downloaded by fw (default: "infineon technologies") dfu: value from eeprom cdc downloaded by fw (default: "infineon technologies") strproduct dfu:"siuc psb2154" cdc: downloaded by fw (default: "siuc psb2154") dfu: value from eeprom cdc downloaded by fw (default: "siuc psb2154") table 33 siuc configuration data for usb descriptors (cont ? d) value no eeprom connected eeprom connected psb 2154 firmware data sheet 336 2001-01-24 note: maxpower: the actual power consumption of the siuc is far below 100 ma, however, the real value was not known at the time of rom mask setting. moreover, external components add further power consumption. therefore the worst case value was set for maxpower to allow low power device operation. strserialnumber dfu:(no string) cdc:downloaded by fw (no default value) dfu: value from eeprom cdc downloaded by fw (no default value) strconfiguration dfu:"dfu" cdc:downloaded by fw (default: "cdc") dfu: value from eeprom cdc downloaded by fw (default: "cdc") table 33 siuc configuration data for usb descriptors (cont ? d) value no eeprom connected eeprom connected psb 2154 firmware data sheet 337 2001-01-24 the configuration data described above is stored in external eeprom in the following format: note: mp = maxpower svn = system version number byte number 14 and 15 must be programmed to the values 55 h and aa h , respectively. this is used by the bootloader firmware to detect whether the connected eeprom has been programmed (i.e. data is valid) or the eeprom is unprogrammed (i.e. data is invalid). in the latter case the eeprom is not read by the firmware and the data is ignored. the total memory space depends on the selected eeprom (e.g. 1024 or 2048 bit) which has effect on the remaining memory space available for propietary extensions. all strings consist of one byte for length information (len) followed by the character information. the actual start position of strings (e.g. strproduct, ...) is not fixed (as shown above) but depends on the length of the preceeding strings, i.e. a string starts after the last byte of the preceeding string. for strings with the length 0 the corresponding index of a descriptor will be set to "no string" (0). table 34 organisation of eeprom memory 0123456789101112131415 0 idvendor idproduct bcd device bcdusb bdc bsc bdp bmat mp svn 55 h aa h 16 len strmanufacturer 32 strmanufacturer (continued) 48 len strproduct 64 strproduct (continued) 80 len strserialnumber len strconfiguration 96 strconfiguration (continued) 112 128 : : 255 = contents not defined and available for propietary extensions (if not used by strings) psb 2154 firmware data sheet 338 2001-01-24 7.5 remote wakeup remote wakeup means an incoming call from the isdn line can wakeup the siuc and the host, both of which are in suspend mode. in order to achieve a reasonably working wakeup functionality it is necessary to support major parts of the d-channel layer 2 and layer 3 protocols (see "implementation hints" below). additionally a power management concept needs to be provided on the system. the firmware provided with the siuc is focused on single chip and low-cost isdn terminal applications and does not include the relevant parts of the d-channel protocol. therefore the siuc-x firmware does not support remote wakeup. however, with external memory extension the wakeup feature can easily be implemented. some guidelines and hints for a possible implementation are given below. implementation hints when the system is in power down mode (usb suspend mode) an incoming call will wakeup the host and the c in the siuc-x. as the response time of the host is considerably high due to the long time the os usually needs to return to operational state, the c handles major parts of the d-channel layer-2 and layer-3 protocol to setup the call and to provide enough time for the host to resume. layer 1 the isdn layer 1, based on the itu standard i.430, is handled mainly by the siuc-x. to be fully compliant to the tbr3 conformance test suite, the software supports additional timers for activation from te side and for delayed deactivation. the siuc-x correctly handles activation from the network (only activation of s transceiver necessary). it is not required that the software is active before a complete wakeup of the siuc-x. note: it is possible that the layer 1 is always activated because the network or other devices on the s-bus prevent the line from deactivation. in this case wakeup can not be triggered by activation of the layer 1 interface. layer 2/3 the layer 2 and 3 are based on the itu standards q.921 and q.931 (or for europe ets 300 125 and ets 300 102-1/ets 300 102-2). the first frame on an incoming call is the layer 3 message setup. the siuc-x decodes this message (only the hdlc receiver is activated). if it is not the right message (e.g. called party number is wrong or not relevant information like time received) the controller ignores it and switches back to suspend mode. after the controller has found a correct and matching setup message it signals resume to the host (activation of usb module). psb 2154 firmware data sheet 339 2001-01-24 until the time the host is available, the siuc answers with an "alert" (layer 3). to do this the software sets up a layer 2 connection for sending layer 3 frames. at this moment the first data has to be sent over the s-bus (the hdlc transmitter is activated). the layer 2 consists of a state machine for q.921 and handling of a tei value (request, assign and verify). power management for the power consumption requirements the usb specification differentiates between low power and high power devices: as high power devices can only be operated at root hubs or self powered hubs, most system architectures for bus powered isdn terminal equipment will be implemented as low power devices. remote wakeup requires the c to handle the call management while the usb host is still in suspend mode. only if a valid incoming call is detected, a wakeup to the host is initiated. so while the usb is still in suspend mode the c is operating which results in a higher power consumption of the device. due to these reasons a reasonably functioning isdn terminal device for usb can only be built as self powered device, otherwise the host would see a remote wakeup with any signal on the s interface. table 35 usb power consumption limits state high power device low power device suspend 2.5 ma 500 a unconfigured 100 ma 100 ma configured 500 ma 100 ma psb 2154 general features data sheet 340 2001-01-24 8 general features 8.1 clock generation the siuc-x derives its system clocks from an external clock connected to xtal1 (while xtal2 is not connected) or from a 7.68 mhz crystal connected across xtal1 and xtal2 ( figure 130 ). a description of the oscillator circuit is provided in chapter 10.5 . 8.1.1 usb / microcontroller the crystal output passes through a programmable pll to generate the 48mhz clock for the usb device controller and the microcontroller. the input / output frequency equation is: n and m can be programmed in the plcona and plconb registers. the default values n=24 d and m=3 d determine the output clock = 25/4 x 7.68 mhz = 48 mhz. programming sequence after reset the pll is disabled and the c is operating at 7.68 mhz crystal frequency. the c sets the factors m and n and enables the pll (pclk). it takes a few ms for the pll to indicate the status "pll locked" (bit lock is set), after which the c can switch the pll clock from "bypass" to "connected" (swck). now the c is operating at 48 mhz. prescaler for the microcontroller clock a prescaler can be used to divide the 48 mhz clock from the pll. if enabled (plconb.pscen=1) the prescaler divides by 2 (plcon.pscval=0) resulting in 24 mhz frequency or it divides by 1.5 (plcon.pscval=1) resulting in 32 mhz frequency. this may be used for test purposes or to reduce power consumption if less c performance is sufficient. usb clock enable after reset the clock for the usb device controller is disabled. as soon as the pll is programmed and provides the 48 mhz clock, the c can switch on the usb clock by setting dcr.uclk. clock output = n+1 m+1 clock input where, n = 0......31 and m = 0......15 psb 2154 general features data sheet 341 2001-01-24 8.1.2 s-transceiver pll the iom clocks are summarized with the respective duty cycles in table 36 . all output clocks are synchronous to the s-transceiver. the fsc signal is used to generate the pulse lengths of the different reset sources software reset, c/i code, eaw pin and watchdog (see chapter 8.2 ). in te applications, the transmit and receive bit clocks are derived, with the help of the pll, from the s interface receive data stream. the received signal is sampled several times inside the derived receive clock period, and a majority logic is used to additionally reduce bit error rate in severe conditions. the transmit frame is shifted by two bits with respect to the received frame. table 36 iom clocks mode dcl fsc bcl te o: 1536 khz (1:1) o: 8 khz (1:2) o: 768 khz (1:1) psb 2154 general features data sheet 342 2001-01-24 figure 130 siuc clock system :(m+1) x(n+1) phase detector & clock dividers divider synchronizer & clock recovery n = 0...31 (24) m = 0...15 (3) 7.68 mhz sx1,sx2 (192 kbps) sr1,sr2 (192 kbps) dcl 1.536mhz (o) fsc 8khz (o) s-transceiver pll usb / microcontroller pll 2154_82.vsd reset generation - sw reset -c/i -eaw - watchdog rsto 125s t 250s xtal1 xtal2 c usb 48 mhz dcr.uclk bcl 768khz (o) 2 1.5 prescaler plconb.pscen plconb.psval psb 2154 general features data sheet 343 2001-01-24 8.1.2.1 receive pll (rpll) the receive pll performs phase tracking between the f/l transition of the receive signal and the recovered clock. phase adjustment is done by adding or subtracting 0.5 or 1 xtal period to or from a 1.536-mhz clock cycle. the 1.536-mhz clock is than used to generate any other clock synchronized to the line. during (re)synchronization an internal reset condition may effect the 1.536-mhz clock to have high or low times as short as 130 ns. after the s/t interface frame has achieved the synchronized state (after three consecutive valid pairs of code violations) the fsc output in te mode is set to a specific phase relationship, thus causing once an irregular fsc timing. the phase relationships of the clocks are shown in figure 131 . figure 131 phase relationships of siuc-x clock signals 8.1.2.2 jitter the timing extraction jitter of the siuc-x conforms to itu-t recommendation i.430 ( ? 7% to + 7% of the s-interface bit period). itd09664 7.68 mhz 1536 khz * 768 khz * synchronous to receive s/t. duty ratio 1:1 normally f-bit fsc psb 2154 general features data sheet 344 2001-01-24 8.2 reset generation 8.2.1 hardware reset operation the external hardware reset forces the chip components to a predefined default state. it must be of at least 4 ms duration to allow the 7.68mhz oscillator to stabilize. the reset input is an active low input (reset ). an internal schmitt trigger is used at the input for noise rejection. following reset, the device performs a complete machine cycle (12 clocks) during which other indirectly reset registers are initialized. an automatic power-on reset can be obtained by a capacitor connected to vss and a resistor connected to vdd. after vdd has been turned on, the capacitor holds the voltage level at the reset pin for a specific time to effect a complete reset. this external reset signal is additionally fed to the multiplexed rsto /sds output if enabled (see chapter 8.2.2 ). the length of the reset signal is specified in the electrical specification . a reset operation of the usb module can only be achieved under software control. 8.2.2 software reset the microcontroller can issue resets through programmable bits to each of the functional blocks ( figure 132 ). they have different functionality compared to the hardware reset. the reset pin is not activated. usb reset the usb module has its own reset bit. this software reset, which must be executed after a hardware reset, is initiated by setting bit dcr.swr by software. this bit is reset automatically by hardware when the software reset operation of the usb module is finished. further, with the reset of bit swr, bit dcr.dinit is set indicating to the cpu to initialize the endpoints of the usb module. a usb reset can also be initiated by the upstream usb port (host or hub controller) issuing a reset signalling on the bus according to the usb specification. c reset the c has its own reset bit, too. bit syscon2.stat1 is required when reconfiguring the device from download mode to firmware execution mode (i.e. switching program execution from rom to ram). psb 2154 general features data sheet 345 2001-01-24 reset output depending on the setting of bits rss1/2 (see mode1 register) several sources can cause a reset of the mode1 register. these reset sources are c/i code change (exchange awake), pin eaw (subscriber awake) and watchdog timeout. additionally, these sources and a reset signal on pin reset can be output on the low active reset output pin rsto . a programmable software reset (sres.res_rsto) is output on pin rsto irrespective of the mode1.rss1/2 setting. watchdog reset if the watchdog timer expires a reset is issued to the siuc-x which has the same effect as a hardware reset (reset pin). after the selection of the watchdog timer (rss2/1 = ? 11 ? ) an internal timer is reset and started. during every time period of 128 ms the c has to program the wtc1- and wtc2 bits in the following sequence to reset and restart the watchdog timer: if not, the timer expires and a wov-interrupt (auxi register) together with a reset pulse of 125 s is generated. it may take a few ms after the interrupt until the the reset is going active. deactivation of the watchdog timer is only possible with a hardware reset, i.e. if rss2,1 is programmed to ? 11 ? the value cannot be reprogrammed again afterwards. in suspend mode all clocks are disabled, so the watchdog is also stopped. however, the watchdog timer continues again when suspend mode is left and clocks are switched on again. it is recommended to write to wtc1,2 according to the above description just before entering suspend mode to avoid the timer to expire accidently right after suspend mode is left again. isdn reset the software reset register (sres) provides reset bits for each functional block of the isdn module. a reset to external devices (pin rsto /sds) can also be controlled in this way. the reset state is activated when the bit is set to ? 1 ? and the reset state is deactivated again automatically. the address range of the registers which will be reset at each sres bit is listed in figure 132 . for the isdn layer-1 state machine, a hardware or software reset (bit res_tr ) brings it to the reset or idle state in which the analog components are disabled (transmission of info 0) and the s/t line awake detector is inactive. reset signals should be a minimum of 2 dcl clock cycles wide. these reset events are identical to the c/i code res with respect to the state machine. wtc1 wtc2 1. 2. 1 0 0 1 psb 2154 general features data sheet 346 2001-01-24 rsto reset source selection the selection of the reset sources on pin rsto can be done with the rss2,1 bits in the mode1 register according to table 37 . if rss2,1 = ? 01 ? the rsto /sds pin has sds functionality and a serial data strobe signal is output at this pin and no reset is output at rsto /sds. the internal reset sources only set the mode1 register to its reset value. c/i code change (exchange awake) a change in the downstream c/i channel (c/i0) generates a reset pulse of 125s t 250s. eaw (subscriber awake) a low level on the eaw input starts the oscillator from the power down state and generates a reset pulse of 125s t 250s. (besides that eaw can also generate an interrupt ista_tr.ld to the c) watchdog timer if the watchdog timer expires a reset is generated as described above. if rss2,1 is programmed to ? 11 ? the value cannot be reprogrammed afterwards, i.e. the watchdog timer can only be stopped again by a reset. sds functionality sds is not related to reset functionality. a serial data strobe signal can be programmed in sds_cr and output on pin rsto /sds (see chapter 5.5.3 ). note: a reset on rsto can always be activated by setting the software reset bit sres.res_rsto irrespective of the mode1.rss1,2 setting (i.e. even if sds functionality is selected). table 37 reset source selection (mode1.rss2,1) rss2 rss1 c/i code change eaw watchdog timer sds functionality 0 0 -- -- -- -- 0 1 -- -- -- x 1 0 x x -- -- 11 -- -- x -- psb 2154 general features data sheet 347 2001-01-24 figure 132 reset generation c/i code change (exchange awake) eaw (subscriber awake) watchdog 1 125s t 250s 125s t 250s software reset register (sres.xx) reset functional blocks reset mode1 register internal reset of all registers 1 rss1 rss2,1 '0' '1' '1x' '00' rss2,1 '01' '01' pin rsto / sds pin reset 2154_83.vsd b-channels (f870 h -f88f h ) d-channel (f820 h -f82f h ) tr (f830 h -f83f h ) iom (f840 h -f85a h ) mon (f85b h -f85f h ) no reset device control register (dcr.swr) usb module system control register2 (sycon2.stat1) microcontroller, sfr registers usb reset (initiated from host) sds signal generation 125s t 250s 125s t 250s no reset rss2,1 '11' '11' ext. software reset (sres.res_rsto) 125s t 250s 1 psb 2154 general features data sheet 348 2001-01-24 8.3 auxiliary interface 8.3.1 mode dependent functions the aux interface provides various functions as shown in table 38 . after reset the pins are switched as inputs until further configuration is done by the microcontroller. the system designer must use this interface with care in case the spi functionality is required simultaneously with other auxiliary functions, for example if an eeprom is connected (chip select signal on aux3). the registers of the auxiliary interface are located in the isdn register map and described in chapter 5.8.3 . aux0-5 these pins can be used as programmable i/o lines. as inputs (aoe.oex=1) the state at the pin is latched in when the host performs a read operation to register arx. as outputs (aoe.oex=0) the value in register atx is driven on the pins with a minimum delay after the write operation to this register is performed. they can be configured as open drain (acfg1.odx=0) or push/pull outputs (acfg1.odx=1). the status ( ? 1 ? or ? 0 ? ) at output pins can be read back from register arx, which may be different from the atx value, e.g. if another device drives a different level. table 38 aux pin functions pin function aux0 aux0 (i/o) aux1 aux1 (i/o) aux2 aux2 (i/o) aux3 aux3 (i/o) / eld (i) / scs (o) aux4 aux4 (i/o) / sdi (i) / mbit (i/o) / svn0 (i) aux5 aux5 (i/o) / sdo (o) / fbout (o) / svn1 (i) aux6 int1 (i/o) / sck (o) aux7 int2 (i/o) / sgo psb 2154 general features data sheet 349 2001-01-24 int1 , int2 and led ports in all modes two pins can be used as programmable i/o with optional interrupt input capability (default after reset, i.e. both interrupts masked). the int1/2 pins are general input or output pins like aux0-5 (see description above). in addition to that, as inputs they can generate an interrupt to the host (auxi.int0/1) which is maskable in auxm.int1/2. the interrupt input is either edge or level triggered (acfg2.el1/2). as outputs both pins can directly be connected to an led with preresistor. for both pins aux6/7 internal pull-up resistors are provided if the pin is configured as input or as output with open drain chracteristic. the internal pull-ups are disabled if output mode with push/pull characteristic is selected. fbout aux5 is multiplexed with the selectable fsc/bcl output fbout, i.e. the host can select either standard i/o characteristic (acfg2.a5sel=0, default) or fbout functionality (acfg2.a5sel=1). fbout provides either an fsc (acfg2.fbs=0, default) or bcl signal (acfg2.fbs=1) which are derived from the dcl clock (also see chapter 8.1 ). sgo aux7 provides the additional capability to output the s/g bit from the iom-2 interface by setting acfg2.a7sel=1. mbit if acfg2.a4sel is set to ? 1 ? the pin aux4 is used for multiframe synchronization output (see chapter 5.2.3 ) and all configuration as general purpose i/o pin is don ? t care. system version number (svn0, 1) these two pins are used as input during reset to latch a logical ? 1 ? (external pull-up resistors required) or ? 0 ? (internal pull-downs provided) to the svn0, 1 bits in register hcon. the firmware transfers this information to the host so the system configuration built around the siuc can be identified by the host and the appropriate firmware and software drivers can be loaded. for further information refer to chapter 7.2 . spi-signals (eld, sdi, sdo, sck, scs ) these signals are multiplexed with the functions described above. as long as the spi interface is not accessed by activating the chip select signal scs , the non-spi functionality is available. the spi interface is described in detail in chapter 8.3.2 . psb 2154 general features data sheet 350 2001-01-24 8.3.2 spi interface the siuc-x includes a serial peripheral interface bus to connect an external eeprom. this eeprom can optionally be used to load any vendor specific data. the physical interface for the eeprom is a serial 3-wire interface to connect standard memory devices like 25c20, supporting devices up to 4k. the following signals are used: sdi, sdo, sck during all eeprom transactions, these pins are used as data input pin, data output pin and clock pin, respectively. the clock signal is driven by siuc-x. data is clocked out on the negative edge of sck and clocked in on the positive edge of sck. scs this is the active low chip select pin for the eeprom. eld this pin is strapped during the hardware reset and stored in the eepsl register to indicate to the c that usb ids should be loaded from eeprom after reset. a logic 1 indicates to the c whether an eeprom is connected. if set to 1, the c will read the ids from the external eeprom and load the corresponding id registers. if set to 0 no eeprom access is performed and the id registers are loaded with default values. during normal operation, a connected eeprom can be accessed through the eeprom configuration registers, e.g. to read/write any proprietary data irrespective of the state of eld after a reset. figure 133 spi read access 2154_43 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122 8 6 5 4 3 2 1 70 6 5 4 3 2 1 70 23 high impedant address bits instruction byte address data read scs sck sdo sdi psb 2154 general features data sheet 351 2001-01-24 figure 134 spi write access 8.3.2.1 direct microcontroller access to the eeprom eeprom configuration registers are implemented to enable access to the eeprom directly. for example, the microcontroller can write the eeprom contents during board manufacturing and read back the contents for verification or it can use the eeprom to store customized information. to control all eeprom transactions the following registers are used. the registers are located at address 93h - 97h in the special function register address space. eepcmd - eeprom command register the microcontroller writes the command for the next eeprom transfer to this register. the following spi commands are supported (all other codings are reserved): ? 00000110 ? ? wren,set write enable latch ? 00000100 ? ? wrdi,reset write enable latch ? 00000101 ? ? rdsr,read status register ? 00000001 ? ? wrsr,write status register ? 0000a011 ? ? read,read data from memory array ? 0000a010 ? ? write,write data to memory array "a" represents the msb address bit a8, the lower 8 bits (a7-0) is contained in the eeprom byte address register eepadr. eepadr - eeprom byte address register for read and write transactions to the connected eeprom, the eeprom byte address is written to this register before the transaction is started. the msb address bit a8 is contained in the eeprom command register eepcmd. eepdat - eeprom data register for the transactions 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122 8 6 5 4 3 2 1 70 6 5 4 3 2 1 70 23 high impedant address bits instruction byte address data write scs sck sdo sdi 2154_43 psb 2154 general features data sheet 352 2001-01-24 - ? write status register - wrsr ? and - ? write data to memory array - write ? the data that has to be transferred to the eeprom is written to this register before the transaction is started. after the transactions - ? read status register - rdsr ? or - ? read data from memory array - read ? are finished (esta bit is reset and an interrupt is generated), the byte received from the eeprom is available in this register. esta - eeprom start bit the microcontroller sets this bit to ? 1 ? in order to start an eeprom transaction. it must be ensured that the eepcmd, eepadr and eepdat registers are configured with the correct values before the transaction is started. after the transaction is finished the esta bit is reset by hardware and an eeprom control interrupt ecint is released to the microcontroller (if enabled in register ien0). to start a read/write transaction to a connected eeprom, the microcontroller sets the eeprom command eepcmd, the eeprom byte address eepadr (for eeprom read/write data commands), the data eepdat that is to be written to the eeprom and finally sets the eeprom start bit esta. the eeprom command is then interpreted and the siuc-x starts the read/write transaction to the connected eeprom. after the transaction has finished, the esta bit is reset to ? 0 ? and an ecint interrupt is generated to the c (eepint-eeprom interrupt control register), if the interrupt is enabled (ien0.es=1). if the eeprom command is a read command (read status register, read data from memory array), the byte that is read out of the eeprom is available in the eepdat register when the transfer is finished. psb 2154 general features data sheet 353 2001-01-24 8.3.3 spi registers the eeprom interrupt control register (eepint) is described in the section on interrupts. 8.3.3.1 eepcmd - eeprom command register resetvalue:00 h address: 94 h 76543 210 .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw bit function eepcmd.7 - eepcmd.0 eeprom command command for the next eeprom transaction. the following spi commands are supported: ? 00000110 ? ? wren,set write enable latch ? 00000100 ? ? wrdi,reset write enable latch ? 00000101 ? ? rdsr,read status register ? 00000001 ? ? wrsr,write status register ? 0000a011 ? ? read,read data from memory array ? 0000a010 ? ? write,write data to memory array "a" contains the msb address bit a8 for read/write transactions. psb 2154 general features data sheet 354 2001-01-24 8.3.3.2 eepadr - eeprom byte address register resetvalue:00 h address: 95 h 8.3.3.3 eepdat - eeprom data register resetvalue:00 h address: 96 h 76543 210 .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw bit function eepadr.7 - eepadr.0 eeprom byte address byte address for the next eeprom transaction. the msb address bit a8 for read/write transactions is contained in the eeprom command byte (see above). 76543 210 .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw rw rw rw bit function eepdat.7 - eepdat.0 eeprom data transaction with a read command: after the transaction has finished, the register contains the byte that has been read from the eeprom. transaction with a write command: the contents of this register will be written at the relevant eeprom address, after the esta start bit is set. psb 2154 general features data sheet 355 2001-01-24 8.3.3.4 eepsl - eeprom start / load register resetvalue:00 h address: 97 h 7654321 0 eld 0 0 0 0 0 0 esta rrrrrrrrw bit function eld eeprom load the eld pin is latched with the falling edge of reset. a logic 1 (which overwrites the internal pulldown resistor) indicates that an eeprom is connected to the siuc-x and that the c could load usb ids from it. esta eeprom start bit setting this bit to ? 1 ? starts an eeprom transaction with the eeprom command, eeprom data and the eeprom byte address. after the transaction is finished, this bit is reset by hardware to indicate that another transaction may be started by the microcontroller. psb 2154 general features data sheet 356 2001-01-24 8.4 voltage regulator the siuc provides an onchip voltage regulator which allows direct connection to the power lines of the usb port using some external components. in this way bus powered operation without an external voltage regulator can be realized. the functional part of the siuc is isolated from the onchip regulator, so the regulated output voltage must be connected to the power supply pins of the siuc. further devices (e.g. external sram) can be connected as long as the total power budget of the regulator is not exceeded. figure 135 shows how the external components are to be connected to the vreg1/2 pins. if self-powered operation is required (separate power supply) the voltage regulator is not used and its pins vreg1/2 are left open. figure 135 external circuitry of the voltage regulator note: the figure does not show any general power supply requirements such like blocking capacitors. c2 vreg2 vreg1 c1 voltage regulator voltage reference + - t +3.3v output to the rest of the logic r +5v input from usb siuc vddx vddx vddx vddx vddx vddx vddx (vddx = vdd, vdda, vddap, vddu) 2154_31 vssx vssx vssx vssx vddx vssx vssx vssx vssx vssar gnd d- d+ vbus usb connector (vssx = vss, vssa, vssap, vssu) psb 2154 operational description data sheet 357 2001-01-24 9 operational description 9.1 configuration of functional blocks this chapter contains a description how the functional blocks of the siuc must be programmed after reset. a detailed description in which sequence the programming is to be done can be found in chapter 9.3 . on the right side the relevant pins, registers (in bold), register bits and cross references for a detailed description are given: firmware operation mode after a reset of the siuc-x, the microcontroller starts operation depending on the strapping of the ea and bmod pins. for this purpose the value of the bmod pins is available in the internal special function register hcon (hardware configuration register). in eprom mode firmware execution directly starts from external memory (ea =0). in downalod mode (ea =1) the bootloader in rom is executed first and only after the firmware download is finished, execution of operational firmware starts. hcon bmod0/1 ea , (p. 65, 318) pll configuration right after reset the pll is bypassed and the c is operating at crystal speed 7.68 mhz. the pll must be programmed before operation at 48 mhz is possible. plcona/b m3-0, n4-0, pclk, lock, swck (p. 340, 66) usb clock enable after the pll is programmed (see above) the 48 mhz clock for the usb device core (udc) must be enabled by setting uclk. dcr .uclk (p. 340, 113) internal memory access enable in order to enable access to onchip ram the xmap0 bit must be set. syscon1 .xmap0 (p. 42, 71) ale output disable for access to onchip ram the output of the ale signal must be disabled. syscon1 .eale (p. 42, 71) psb 2154 operational description data sheet 358 2001-01-24 the description above contains a minimum set of configuration registers that is loaded with specific values. other configuration registers may optionally be programmed depending on the required features and operating modes, that means the siuc has reached normal operation mode and the usb and isdn parts can be programmed to operate in the way required by the individual application. the microcontroller may switch between power-up and suspend mode. this does not influence the register contents, i.e. the internal states remain stored. in suspend mode however, all internal clocks are disabled, and no interrupts can be forwarded to the microcontroller. this state is used as a standby mode, when there is no activity on either the usb or the s-interface, thus minimizing power consumption. the device can be waked up from this suspend state by different sources which can be enabled before entering suspend mode (see chapter 9.3.6 ). the communication between the microcontroller and iom-2, s-interface is done via a set of directly accessible 8-bit registers. the microcontroller sets the operating modes, controls function sequences and gets status information by writing or reading these registers (command/status transfer). each of the two b-channels is controlled via an equal, but totally independent register file. additional registers are available for d- channel control and the auxiliary interface. data transfer between the microcontroller memory, iom-2, s-interface and usb for both transmit and receive direction is controlled by interrupts. switching of memory control signals for download mode and for certain memory configurations the control signals (rd , wr , psen , pwr ) of the external memory interface need to be switched. syscon1/2 stat0, scs (p. 41, 71, 73) program and data ram partitioning after download is finished and firmware execution is switched from rom to ram, the partitioning of internal ram into program and data ram (single chip applications) must be done via the registers psiz and dsiz. psiz dsiz (p. 43, 69, 70) switching program execution from rom to ram in download mode the bootloader performs the download to internal/external ram. when this is finished program execution is switched from rom to ram which is done by first setting stat2 to switch from rom to ram and then setting stat1 to reset the c. syscon2 stat1, stat2 (p. 43, 73) psb 2154 operational description data sheet 359 2001-01-24 special events from the isdn module are indicated by means of a 8 interrupt outputs, which requests the microcontroller to read status information or transfer data. events on the usb interface are indicated by means of 2 interrupts. 9.2 power saving modes the siuc-x provides two power saving modes: ? idle mode ? suspend mode if the suspend mode and the idle mode are set at the same time, suspend takes precedence. this chapter contains a general overview on the power saving modes, chapter 9.3 describes the sequence of operations to reach these modes. 9.2.1 idle mode the idle mode is characterized by the following behaviour: the oscillator continues to run the c is gated off from the clock signal the rest of the modules are still provided with the clock the c status is preserved in its entirety (i.e. stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode) the reduction of power consumption, which can be achieved by this feature depends on the number of peripherals running. if all the peripherals are disabled or stopped, maximum power reduction can be achieved. the idle mode is a useful feature which makes it possible to "freeze" the processor ? s status - either for a predefined time, or until an external event reverts the controller to normal operation. the following functions can optionally be disabled to achieve several levels for power consumption in idle mode: the idle mode is configured in the pcon register in the following way. first the idle_mode_enable bit idle is set and with the following instruction the idle_start bit idls is set. pcon idle, idls (p. 62) psb 2154 operational description data sheet 360 2001-01-24 usb transmitter power down the transmitter can be disabled by setting tpwd which is usefull if no data is sent on the usb but receive data is still monitored on the bus. dpwdr tpwd (p. 115) usb receiver power down the receiver can be disabled by setting rpwd which is usefull if no data needs to be received from the bus. however, if wakeup from usb (i.e. resume initiated by the host) should wakeup the c, the receiver should not be powered down. dpwdr rpwd (p. 115) usb clock disable the clock for the usb controller can be disabled by resetting uclk, so the usb part is in its lowest power down state. dcr uclk (p. 113) isdn functions power down as the isdn module is still provided with clocks in idle mode any of the functional units (transceiver, iom-2, hdlc controllers) which are all disabled for suspend mode (clocks are off) can individually be disabled to reduce power consumption (see chapter 9.2.2.1 ). however, the level detect circuit of the transceiver must be enabled if incoming calls from the line should be detected. psb 2154 operational description data sheet 361 2001-01-24 9.2.2 suspend mode in order so switch the siuc to suspend mode (power down mode) special care must be taken when switching off the clocks. several conditions must be met so the oscillator can be powered down ( figure 136 ). figure 136 clocks in suspend mode the following programming procedure must be followed to reach suspend state: disable iom clocks in power down mode (mode1.cfs=1) and set layer 1 state machine to "deactivated state" (write the c/i command di and wait for c/i indication dc). enable the sources that can wakeup siuc from suspend mode (wcon register). if no wakeup sources are enabled, the suspend mode can only be left by a reset. set usb transmitter to power down mode (dpwdr.tpwd=1). do not set usb receiver to power down mode (dpwdr.rpwd=0) if wakeup from usb (resume on the bus) should be possible. then switch off the usb clock (dcr.uclk=0). first the pll is switched to bypass mode (plconb.swck=0), i.e. the c operates at crystal speed 7.68 mhz, and then the pll for usb and c is switched off (plconb.pclk=0). finally the microcontroller switches itself to suspend mode by first writing pcon.sme=1 and with a successive access setting pcon.sms=1. only with the last access the oscillator is finally powered down. mode1 .cfs c/i = diu, dc (p. 277) wcon (p. 368 ) dpwdr tpwd, rpwd, (p. 115) dcr .uclk (p. 113) plconb swck, pclk (p. 66) pcon sme, sms (p. 62) 2154_49 osc =1 pll isdn usb c isdn: mode1.cfs=1 isdn: state machine in deactivated state c: pcon.sms=1 c: plconb.swck / pclk psb 2154 operational description data sheet 362 2001-01-24 the suspend mode is characterized by the following behaviour: the xtal oscillator is deactivated all functions of the microcontroller are stopped only the contents of the onchip iram, xram and sfrs are maintained all internal pull up and pull down resistors are switched off the usb module enters the suspend state when it detects no activity on the usb bus for more than 3 ms. the suspend mode can be left in one of the following ways which is enabled in the wcon register (also see chapter 6.3 and chapter 9.3.6 ): a low signal at pin p3.1/int0 , int1 , int2 or eaw a c/i code change any activity on the s bus any activity on the usb bus an active reset signal at reset if the suspend state is left due to one of the events described above (except "reset") the device is waked up. using the reset to leave suspend mode puts the microcontroller with its sfrs into the reset state. using any of the other sources to exit the suspend mode maintains the state of the sfrs, which has been frozen when suspend mode was entered. in suspend mode the internal pull up resistor at int0 is switched off to avoid high leakage current. if int0 is used as wakeup source, the port must be programmed to push pull characteristic, or if open drain characteristic is required, an external pull up must be connected. if int0 is not used as interrupt during suspend, the port should be programmed as output by writing a ? 1 ? to it. if the iom-2 interface is not used in the application system, the open drain characteristic of the data lines du and dd must be disabled (iom_cr.dis_od=1) as the missing pull up resistors would cause malfunction in suspend mode. further information on the topics enabling/disabling certain wakeup sources and on suspend state with disabled wakeup capability can be found in chapter 6.3 . psb 2154 operational description data sheet 363 2001-01-24 9.2.2.1 isdn module power down configuring the suspend mode as described above has no effect on the configuration of the isdn module. the functional blocks there must individually be programmed to power down mode which is done before going into suspend mode. however, setting some of these blocks to power down mode may also be used to implement an idle mode (see chapter 9.2.1 ). power down the isdn module has configuration bits that can initiate a local power down when the rest of the chip is in the active state. there are 2 modes of entering power down: giving the c/i command 1111 = diu - deactivation indication upstream (written to cix0) when the layer-1 state machine is enabled. no signal (info 0) is now present on the s bus (asuming no other device is transmitting on s). setting the tr_cmd.pd bit when the layer-1 state machine is disabled (tr_conf0.l1sw = 1). during power down, if mode1.cfs = 0, clocks to/from the module are active. in this case power up and power down are functionally identical except for the indication pd = 1111 and pu = 0111. if mode1.cfs = 1, only the analog level detector is active and all clocks to/from the module are stopped. cix0 tr_cmd .pd tr_conf0 .l1sw mode1 .cfs wake up wake up can take place either from the exchange or the terminal. if tr_conf0.ldd = 0, activation initiated from the exchange side will cause the clock signal to be provided immediately. if tr_conf0.ldd = 1, the c has to take care of an interrupt caused by the level detect circuit (istatr.ld). the c must then set this bit to 0 to activate the s/t interface again. from the terminal side, wakeup can be initiated by a set/reset of iom_cr.spu and writing tim to the cix0 register or by resetting mode1.cfs. tr_conf0 .ldd istatr .ld iom_cr .spu cix0 mode1 .cfs psb 2154 operational description data sheet 364 2001-01-24 transceiver tr_conf0.dis_tx can be used to disable the transmitter (while the receiver is still active) and tr_conf0.dis_tr disables the complete transceiver resulting in minimum power consumption. in this mode dcl and fsc are inputs. when the s-transceiver is completely switched off, no activation from the line can be detected. to overcome this, the level detect circuit can be enabled before switching off the transceiver (see above). the power consumption is minimal, but only a level on the line is detected, the s-transceiver will not automatically start to setup layer-1. the transceiver has to be switched on first. tr_conf0 dis_tx dis_tr iom-2 iom_cr.dis_iom is used to disconnect external devices from iom-2. setting iom_cr.spu pulls the du line low. this will force connected layer-1 devices to deliver iom clocking. after a subsequent ista.cic interrupt, and reception of the c/i code pu, the c writes an ar or tim command as c/i code in the cix0 register and resets the spu bit. iom_cr dis_iom spu ista .cic cix0 psb 2154 operational description data sheet 365 2001-01-24 9.3 sequence of operations the siuc uses 4 operational states which are reset state (after power on reset, hardware reset) active mode (normal operation) idle mode (chapter 9.2.1) suspend mode (chapter 9.2.2) a well defined procedure must be executed for going from one state to another, so the following state transitions and required sequence of operations are described in the chapters below. reset to active active to idle idle to active active to suspend suspend to active of utmost importance is initialization of the usb module. the previous chapters describe in detail how each functional unit is configured. the following chapters describe the sequence in which configuration has to take place. 9.3.1 reset to active after a hardware reset which lasts 4 ms, all chip components excluding the usb module are initialized. a hardware reset operation puts only the internal c interface of the usb module and its memory management unit into a well defined reset state. the microcontroller starts execution at the 7.68 mhz xtal frequency. the microcontroller executes one machine cycle to reset all indirectly resetable registers. the c programs the pll for the usb module and the c ( chapter 9.1 ). the usb module clock is switched on by programming dcr.uclk ( chapter 9.1 ). setting the usb reset bit dcr.swr starts the software reset operation of the complete usb module. when the software reset is finished, dcr.swr is automatically cleared by hardware and bit dcr.dinit is set to indicate the start of the initialization sequence. the usb module is functionally initialized by the microcontroller by writing the configuration bytes for each endpoint. thereafter, bit epbsn.donen is set by software. after this action, bit dcr.dinit is automatically reset by hardware and the software reset and initialization sequence are finished. programming of required configuration registers (e.g. isdn) takes place. this depends on the required operation mode. psb 2154 operational description data sheet 366 2001-01-24 this switch-on procedure after a hardware reset assures proper operation of the usb clock system. 9.3.2 active to idle this chapter provides a description for the operational sequence, for a detailed description about the idle mode itself please refer to chapter 9.2.1 . the idle mode is entered by programming the bits idle and idls in the pcon register. in idle mode, different sub-modules (e.g. usb module, s-interface, hdlc controllers) can be fully functional or can be switched off depending on system requirements. special care is necessary to switch off the usb module. the following steps must be processed before entering the idle mode: - c switches the usb module clock off by resetting dcr.uclk. - pll output is synchronously switched to low frequency input (plconb.swck=0), i.e. the pll is actually bypassed and the c is operating at 7.68 mhz - pll is switched off (plconb.pclk=0) 9.3.3 idle to active there are two ways to terminate the idle mode hardware reset interrupt hardware reset the hardware reset must be kept active for 4ms till the oscillator stabilizes. the "reset to active" sequence applies now ( chapter 9.3.1 ). interrupt the idle mode is left by receiving any enabled interrupt. this interrupt will be serviced and normally the instruction to be executed following the reti instruction will be the one following the instruction that set the idle bit. after leaving the idle mode through an interrupt (e.g. from the usb module), a well defined procedure must be executed again to switch on the usb module and pll. first the c programs the pll (see chapter 9.1 ). the usb module clock is switched on by programming dcr.uclk ( chapter 9.1 ). the switch off/on procedure assures proper operation of the usb clock system. as opposed to the hardware reset, after an interrupt the usb module does not need to be reconfigured but the previous settings are retained. programming of required configuration registers (e.g. isdn) takes place. this depends on the required operation mode. psb 2154 operational description data sheet 367 2001-01-24 9.3.4 active to suspend this chapter provides a description of the operational sequence, for a detailed description about the suspend mode itself please refer to chapter 9.2.2 . in suspend mode, the oscillator is stopped. therefore all functions of the c are stopped and only the contents of the onchip iram, xram and sfrs are maintained. special care must be taken for configuration of the suspend mode. for a detailed description please refer to chapter 9.2.2 . 9.3.5 suspend to active there are two ways to terminate the suspend mode hardware reset wakeup event hardware reset the hardware reset must be kept active for 4ms till the oscillator stabilizes. the "reset to active" sequence applies now ( chapter 9.3.1 ). wakeup event if the wakeup capability from suspend initiated by certain events is required, this function must be enabled ( chapter 9.3.6 ) prior to setting the power down configuration bit. in normal operation mode and in idle mode these events will set their corresponding interrrupt status bit and can issue a maskable interrupt. however, in suspend mode these wakeup sources are directly routed to the nmi (non-maskable interrupt) and the interrupt status bits are not affected. in case of a wakeup event, the nmi input to the c800 core is activated by hardware. the core then executes an interrupt service routine at 7b h , and continues normal program execution. the following two cases to exit suspend must are differentiated: exit via pin int0 , eaw , c/i-code change or s-bus level detect if the wake-up capability from one of these sources has been selected and if the standard request set_feature remote_wakeup was given before entering suspend mode, any activity from these sources can initiate termination of the suspend state. when the onchip oscillator clock is detected for stable nominal frequency (after approx. 4 ms), a synchronous multiplexer switches this 7.68 mhz clock to the microcontroller. the interrupt address of the first instruction to be executed after wake- up is 007bh. this interrupt will be serviced and normally the instruction to be executed following the reti instruction will be the one following the instruction that set the power down bit. the pll is switched on and the rest of the steps follow the "reset to active" programming sequence. psb 2154 operational description data sheet 368 2001-01-24 exit via the usb (resume from host) any activity on the usb bus (in this case host initiated) will terminate the suspend state. the wake-up procedure now starts with oscillator stabilization. the wake-up trigger signal from the usb module can only be generated if the usb receiver circuitry was enabled in suspend mode ( chapter 9.2.2 ). the rest of the steps follow the "reset to active" programming sequence. 9.3.6 interrupt wakeup control before the c sets the isdn and usb part and finally itself into suspend mode it can determine which external event will be allowed to terminate the suspend state and initiate a resume. the configuration is done in the wakeup control register (wcon) with the following bits: ewpd (external wakup from power down enable) selects if external wakeup from power down mode is generally enabled, the other bits in register wcon enable the wakeup source individually. if ewpd is configured to "wakeup disabled" all other configuration bits are don ? t care. wpus (wakeup via usb bus enable) wakeup from usb device core wakes up the siuc, i.e. a resume signalling on the bus initated from the usb host is detected. the usb suspend mode end interrupt is indicated in dirr.sei. wpio (wakeup via int0 enable) an external device activating pin p3.1/int0 wakes up the siuc. an external interrupt on int0 is indicated in tcon.ie0. wptr (wakeup via s transceiver enable) any signal level different from info0 (info0 = no signal) indicates an incoming call on the s interface, so the siuc is waked up to receive the call. a level detect interrupt is indicated via ista.tran. wpci (wakeup from c/i-code change or from eaw enable) a code change in the downstream c/i channel or an external awake signal on pin eaw wakes up the siuc. the interrupt is indicated in ista.cic or in ista.aux, respectively. psb 2154 electrical characteristics data sheet 369 2001-01-24 10 electrical characteristics 10.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. voltage applied to any signal pin without the power supply connected can damage the device, i.e. it must be ensured that power supply is connected before any pin signal and the supply voltage must show a monotonic rise. if not otherwise noted in this chapter 10, v dd is used synonymous for v dd , v dda , v ddap , v ddu and v ddr , and v ss is used synonymous for v ss , v ssa , v ssap , v ssu and v ssar . parameter symbol limit values unit min. max. ambient temperature under bias t a 070 c storage temperature t stg ? 55 150 c input/output voltage on any pin with respect to ground v s ? 0.3 5.25 v maximum voltage on any pin with respect to ground v max 5.5 v psb 2154 electrical characteristics data sheet 370 2001-01-24 10.2 dc characteristics v dd / v ss = 3.3v 0.2v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. h-input level (except pin sr1/2) v ih 2.0 5.25 v l-input level (except pin sr1/2) v il ? 0.3 0.8 v h-output level (except pin xtal2, sx1/2) v oh 2.4 v i oh = - 400 a l-output level (except pin xtal2, sx1/2) v ol 0.45 v i ol = 6 ma (du, dd, c768) i ol = 4.5 ma (acl , aux6, aux7) i ol = 2 ma (all others) input leakage current output leakage current (all pins except sx1/2, sr1/2, xtal1/2, aux7/6) i li i lo 1 1 a a 0v< v in psb 2154 electrical characteristics data sheet 372 2001-01-24 10.3 voltage regulator t a = 0 to 70 c figure 137 voltage regulator circuit t = bss129 or bss149(n-channel depletion) r v = 1 ? c1 = 33 f c2= 100 nf r pu = 1.5 k ? 5% (pull up resistor on d+ to indicate a full speed device; r pu is not required for the voltage regulator) parameter symbol limit values unit conditions min. max. input voltage v in 4.10 5.30 v output voltage v out 3.10 3.50 v quiescent current i q 65 a output current - suspend i out1 435 a the output current in operational mode depends on the external circuitry. examples are given below: output current - operational i out2 80 100 ma ma v in = 4.10 v bss129 bss149 c2 c1 t +3.3v regulated output voltage r v +5v (nominal) input from usb vssx gnd d- d+ vbus usb connector d- d+ vssar vreg2 vreg1 vddx r pu vdd vss to further devices on system board (e.g. sram) 2154_31 psb 2154 electrical characteristics data sheet 373 2001-01-24 10.4 capacitances t a = 25 c, v dd = 3.3v 0.2v, v ss = 0 v, f c = 1 mhz, unmeasured pins grounded. parameter symbol limit values unit remarks min. max. input capacitance i/o capacitance c in c i/o 7 7 pf pf all pins except sx1,2 and xtal1,2 output capacitance against v ss c out 10 pf pins sx1,2 load capacitance c l 40 pf pins xtal1,2 psb 2154 electrical characteristics data sheet 374 2001-01-24 10.5 oscillator specification recommended oscillator circuits figure 138 oscillator circuits crystal specification note: the load capacitance c l depends on the recommendation of the crystal specification. typical values for c l are 22 ... 33 pf. xtal1 clock characteristics (external oscillator input) parameter symbol limit values unit frequency f 7.680 mhz frequency calibration tolerance max. 100 ppm load capacitance c l max. 40 pf oscillator mode fundamental parameter limit values min. max. duty cycle 1:2 2:1 its09659 7.68 mhz xtal1 xtal2 xtal2 xtal1 n.c. oscillator external signal crystal oscillator mode driving from external source 42 41 41 42 pf 33 33 pf c l l c psb 2154 electrical characteristics data sheet 375 2001-01-24 10.6 recommended transformer specification parameter symbol limit values unit test condition min. typ. max. transformer ratio 1:1 main inductance l 25 20 mh mh no dc current, 10 khz 2.5 ma dc current, 10 khz leakage inductance l l 8h10 khz capacitance between primary and secondary side c80pf1 khz copper resistance r 1.7 2.0 2.3 w psb 2154 electrical characteristics data sheet 376 2001-01-24 10.7 ac characteristics t a = 0 to 70 c, v dd = 3.3 v 5 % inputs are driven to 2.4 v for a logical "1" and to 0.45 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 139. figure 139 input/output waveform for ac tests its09660 = 100 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf psb 2154 electrical characteristics data sheet 377 2001-01-24 10.8 iom-2 interface timing figure 140 iom ? timing (te mode) parameter symbol limit values unit min. max. iom output data delay t iod 100 ns iom input data setup t iis 20 ns iom input data hold t iih 20 ns fsc strobe delay t fsd -130 ns strobe signal delay t sdd 120 ns bcl delay t bcd 100 ns frame sync setup t fss 50 ns frame sync hold t fsh 30 ns frame sync width t fsw 40 ns itd09663 t fsd t iis iih t t iod bcd t bcd t sdd t fsc (o) dcl (o) du/dd (i) du/dd (o) sds (o) fsc/bcl (o) bcl (0) psb 2154 electrical characteristics data sheet 378 2001-01-24 dcl clock characteristics figure 141 definition of clock period and width symbol limit values unit test condition min. typ. max. t po 585 651 717 ns osc 100 ppm t who 260 325 391 ns osc 100 ppm t wlo 260 325 391 ns osc 100 ppm 2.3 v psb 2154 electrical characteristics data sheet 379 2001-01-24 10.9 memory interface timing - normal mode this chapter specifies the timing of the memory interface in normal operation mode with connected memory for program and data access. during successive accesses to external memory, the cs signal is not toggling but is kept active permanently. if an internal access (e.g. access to isdn registers) is followed by an external access, the cs timing is as shown in figure 142 , figure 143 and figure 144 . figure 142 program memory read cycle - normal mode parameter symbol limit values unit min max address cycle time t cyc 120 ns cs delay from address t csd 3ns address setup to psen t as 40 ns address access time t aa 75 ns psen pulse width t ppw 55 ns psen access time t pa 35 ns instruction data hold after psen t dh 0ns instruction data float after psen t df 50 ns 2154_40.vsd a0-a7 a8-a15 instr. in port 0 a0-7 port 2 cs psen t csd t aa t pa t ppw t cyc t df t as high-z t dh psb 2154 electrical characteristics data sheet 380 2001-01-24 figure 143 data memory read cycle - normal mode parameter symbol limit values unit min max address cycle time t cyc 240 ns cs delay from address t csd 3ns address setup to rd t as 80 ns address access time t aa 155 ns read data hold after rd t dh 0ns read data float after rd t df 38 ns rd pulse width t rpw 110 ns rd access time t ra 75 ns 2154_40.vsd data in port 0 a0-7 port 2 cs rd t csd t aa t ra t rpw t cyc t df t as high-z t dh psen a0-a7 a8-a15 psb 2154 electrical characteristics data sheet 381 2001-01-24 figure 144 data memory write cycle - normal mode note: during firmware download via usb the c performs write accesses to external program memory if connected. the timing conditions for this mode of operation is the same as shown in figure 144 with the exception that the pwr signal (program write) is used instead of wr . read parameter symbol limit values unit min max address cycle time t cyc 240 ns cs delay from address t csd 3ns address setup to wr t as 80 ns wr pulse width t wpw 110 ns write data setup time t ds 50 ns write data hold time t dh 5ns 2154_40.vsd data out port 0 a0-7 port 2 cs wr / pwr t csd t wpw t cyc t as high-z t dh psen a0-a7 a8-a15 t ds psb 2154 electrical characteristics data sheet 382 2001-01-24 10.10 memory interface timing - emulation mode figure 145 program memory read cycle - emulation mode mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav psb 2154 electrical characteristics data sheet 383 2001-01-24 figure 146 data memory read cycle - emulation mode mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph psb 2154 electrical characteristics data sheet 384 2001-01-24 figure 147 data memory write cycle - emulation mode parameter symbol limit values unit min max ale pulse width t lhll 35 ns address setup to ale t avll 10 ns address hold after ale t llax 10 ns ale low to valid instruction in t lliv 50 ns ale to psen t llpl 10 ns pulse width of psen t plph 55 ns psen to valid instruction in t pliv 30 ns input instruction hold after psen t pxix 0ns address valid after psen t pxav 20 ns mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph psb 2154 electrical characteristics data sheet 385 2001-01-24 input instruction float after psen t pxiz 20 ns address to valid instruction in t aviv 60 ns address float to psen t azpl - 5 ns rd pulse width t rlrh 110 ns wr pulse width t wlwh 110 ns address hold after ale t llax2 10 ns rd to valid data in t rldv 75 ns data hold after rd t rhdx 0ns data float after rd t rhdz 38 ns ale to valid data in t lldv 80 ns address to valid data in t avdv 80 ns ale to wr or rd t llwl 55 75 ns wr or rd high to ale high t whlh 12 20 ns data valid to wr transition t qvwx 2ns data setup before wr t qvwh 20 ns data hold after wr t whqx 5ns address float after rd t rlaz 0ns address to valid wr or rd t avwl 60 ns parameter symbol limit values unit min max psb 2154 electrical characteristics data sheet 386 2001-01-24 10.11 auxiliary interface timing the pins from the auxiliary interface can be used as standard i/o pins. their timing conditions either as input or as output is shown in figure 148 . the read and write signals shown below indicate the corresponding access to the siuc register, they are not control signals on the auxilliary interface. figure 148 aux interface i/o timing parameter symbol limit values unit min. max. auxiliary input data setup t ais 30 ns auxiliary input data hold t aih 30 ns auxiliary output data delay t aod 200 ns valid state aux0-7 (i) read from arx t ais t aih write to atx valid state aux0-7 (o) t aod aux input aux output 2115_05 psb 2154 electrical characteristics data sheet 387 2001-01-24 10.12 spi interface timing some pins from the auxiliary interface can be used to realize an spi interface in order to connect a serial eeprom. figure 149 aux interface i/o timing parameter symbol limit values unit min. max. chip select setup time t css 500 ns chip select hold time t csh 500 ns chip select inactive t csi 500 ns clock cycle time t cyc 1000 ns clock high time t clh 410 ns clock low time t cll 410 ns clock output rise time t or 2ns clock output fall time t of 2ns input data setup time t isu 100 ns input data hold time t iho 100 ns output data setup time t osu 500 ns output data hold time t oho 0 500 ns output disable time t od 500 ns write cycle time t wc 10 ns psb 2154 electrical characteristics data sheet 388 2001-01-24 10.13 usb transceiver characteristics the electrical characteristics of the usb device core in siuc are compliant to the usb v1.1 specification. v ddu = 3.3 v 0.2 v, v ssu = 0 v, t a = 0 to 70 c note: 1) this value includes an external resistor of 30 ? 1 % (for testing details see diagram ? load for d+/d- ? ). 2) the crossover point in in the range of 1.3v to 2.0v with a 50 pf capacitance. figure 150 load for d+/d- parameter symbol limit values unit test condition min. max. output impedance (high state) r dh 28 43 ? 1) output impedance (low state) r dl 28 51 ? input leakage current i i 5av in =v ss or v cc tristate output off-state current i oz 10 a v out =v ss or v cc 1) crossover point v cr 1.3 2.0 v 2) parameter symbol limit values unit min. max. rise time t fr 420ns fall time t ff 420ns 2154_86 30 k ? 15 k ? d.u.t. s1 test point 1.5 k ? 2.8 v 50 pf test s1 d- open d+ closed psb 2154 electrical characteristics data sheet 389 2001-01-24 receiver sensitivity the input sensitivity is at least 200 mv when both differential data inputs are in the differential common mode range of 0.8v to 2.5v. figure 151 differential input sensitivity range 10.14 reset figure 152 reset signal parameter symbol limit values unit test conditions min. length of active high state t res 4 ms power on/power down to power up (standby) 2 x dcl clock cycles during power up (standby) 2154_84.vsd 1.01.21.41.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 0.0 0.2 0.4 0.6 0.8 -0.2 differential output crossover voltage range differential input voltage range 2154_52 reset t res psb 2154 package outlines data sheet 390 2001-01-24 11 package outlines p-mqfp-80-1 (plastic metric quad flat package) gpm05249 sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm smd = surface mounted device psb 2154 data sheet 391 2001-01-24 a a4sel bit . . . . . . . . . . . . . . . . . . . . . 254 a5sel bit . . . . . . . . . . . . . . . . . . . . . 254 a7sel bit . . . . . . . . . . . . . . . . . . . . . 254 absolute maximum ratings . . . . . . . 369 ac bit . . . . . . . . . . . . . . . . . . . . . . . . . 63 ac characteristics . . . . . . . . . . . . . . 376 acc register . . . . . . . . . . . . . . . . . . . 68 acfg1 register . . . . . . . . . . . . . . . . 254 acfg2 register . . . . . . . . . . . . . . . . 254 ackn bit . . . . . . . . . . . . . . . . . . . . . . 301 ackxy bits . . . . . . . . . . . . . . . . . . . . 270 acl bit . . . . . . . . . . . . . . . . . . . . . . . 254 activation . . . . . . . . . . . . . . . . . . . . . 155 activation indication - pin acl . . . . . 128 activation led . . . . . . . . . . . . . . . . . 128 activation/deactivation of iom-2 interface . . . . . . . . . . . . . . . . 194 active to idle . . . . . . . . . . . . . . . . . . 366 active to suspend . . . . . . . . . . . . . . 367 address mapping . . . . . . . . . . . . . . . . 30 adroff register . . . . . . . . . . . . . . . 111 aien bit . . . . . . . . . . . . . . . . . . . . . . 309 ale output disable . . . . . . . . . . . . . . 357 an6-3 bits . . . . . . . . . . . . . . . . . . . . . 122 ao5-0 bits . . . . . . . . . . . . . . . . . . . . 111 aoe register . . . . . . . . . . . . . . . . . . 256 applications . . . . . . . . . . . . . . . . . . . . . 8 ar7-0 bits . . . . . . . . . . . . . . . . . . . . 256 arx register . . . . . . . . . . . . . . . . . . 256 as bit . . . . . . . . . . . . . . . . . . . . . . . . 112 asti register . . . . . . . . . . . . . . . . . . 270 at7-0 bits . . . . . . . . . . . . . . . . . . . . 257 attach detection . . . . . . . . . . . . . . . . 102 atx register . . . . . . . . . . . . . . . . . . . 257 aux bit . . . . . . . . . . . . . . . . . . . 275, 305 auxi register . . . . . . . . . . . . . . . . . . 276 auxiliary interface . . . . . . . . . . . . . . 348 timing . . . . . . . . . . . . . . . . . . . . 386 auxm register . . . . . . . . . . . . . . . . . 277 b b register . . . . . . . . . . . . . . . . . . . . . . 68 bac bit . . . . . . . . . . . . . . . . . . . . . . . 242 bas bit . . . . . . . . . . . . . . . . . . . . . . . 241 bchx_cr registers . . . . . . . . . . . . . 263 bchx_tsdp_bc1/2 registers . . . . . 258 block diagram . . . . . . . . . . . . . . . . . . 125 bmod1/0 bits . . . . . . . . . . . . . . . . . . . 65 boot loader firmware . . . . . . . . . . . . 319 boot mode selection . . . . . . . . . . . . . 318 buffer underrun/overflow (usb) . . . . . 90 bulk transfer . . . . . . . . . . . . . . . . . . . . 76 bus bit . . . . . . . . . . . . . . . . . . . . . . . 244 bus-powered mode . . . . . . . . . . . . . 102 c c/i channel . . . . . . . . . . . . . . . . . . . . 185 c/nt1/0 bits . . . . . . . . . . . . . . . . . . . . 58 c/r bit . . . . . . . . . . . . . . . . . . . 239, 290 c800 . . . . . . . . . . . . . . . . . . . . . . . . . . 27 capacitances . . . . . . . . . . . . . . . . . . 373 cbfn bit . . . . . . . . . . . . . . . . . . . . . . 120 cda_tsdpxy registers . . . . . . . . . . 258 cdax_cr register . . . . . . . . . . . . . . 260 cdaxy registers . . . . . . . . . . . . . . . . 257 cdc - communication device class . . . . . . . . . . . . . . . . . . . . . . . . . 331 cfg bit . . . . . . . . . . . . . . . . . . . . . . . 112 cfs bit . . . . . . . . . . . . . . . . . . . . . . . 277 ci_cs bit . . . . . . . . . . . . . . . . . . . . . 268 ci1e bit . . . . . . . . . . . . . . . . . . . . . . . 242 ciar register . . . . . . . . . . . . . . . . . . 112 ciari register . . . . . . . . . . . . . . . . . . 304 ciarie register . . . . . . . . . . . . . . . . . 310 cic bit . . . . . . . . . . . . . . . . . . . 275, 305 cic1/0 bits . . . . . . . . . . . . . . . . . . . . 241 cicw bit . . . . . . . . . . . . . . . . . . . . . . 242 cir0 register . . . . . . . . . . . . . . . . . . 241 cir1 register . . . . . . . . . . . . . . . . . . 242 cix0 register . . . . . . . . . . . . . . 242, 363 psb 2154 data sheet 392 2001-01-24 cix1 register . . . . . . . . . . . . . . . . . . 243 clkm bit . . . . . . . . . . . . . . . . . . . . . 268 clock generation . . . . . . . . . . . . . . . 340 s-transceiver pll . . . . . . . . . . . 341 usb/microcontroller . . . . . . . . . 340 clrepn bit . . . . . . . . . . . . . . . . . . . 120 cmdr register . . . . . . . . . . . . . . . . . 231 cmdrb register . . . . . . . . . . . . . . . . 284 cnt bits . . . . . . . . . . . . . . . . . . 235, 280 codr0 bits . . . . . . . . . . . . . . . . . . . 241 codr1 bits . . . . . . . . . . . . . . . . . . . 242 codx0 bits . . . . . . . . . . . . . . . . . . . 242 codx1 bits . . . . . . . . . . . . . . . . . . . 243 configuration of functional blocks . . 357 control of layer-1 . . . . . . . . . . . . . . . 145 control transfer . . . . . . . . . . . . . . 76, 96 controller data access . . . . . . . . . . . 162 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . 27 crc bit . . . . . . . . . . . . . . . . . . 239, 290 crystal specification . . . . . . . . . . . . . 374 cy bit . . . . . . . . . . . . . . . . . . . . . . . . . 63 d d_en_b2/1 bits . . . . . . . . . . . . . . . . 264 d_en_d bit . . . . . . . . . . . . . . . . . . . 264 d2-0 bits . . . . . . . . . . . . . . . . . . . . . . 60 da bit . . . . . . . . . . . . . . . . . . . . . . . . 113 dai bit . . . . . . . . . . . . . . . . . . . . . . . 299 daie bit . . . . . . . . . . . . . . . . . . . . . . 308 data memory . . . . . . . . . . . . . . . . . . . 32 dbmn bit . . . . . . . . . . . . . . . . . . . . . 119 dc characteristics . . . . . . . . . . . . . . 370 dch_inh bit . . . . . . . . . . . . . . . . . . 253 d-channel access control s-bus priority mechanism . . . . 190 d-channel access control tic bus . . . . . . . . . . . . . . . . . . . 188 dci_cr register . . . . . . . . . . . . . . . 264 dcl clock characteristics . . . . . . . . 378 dcr register . . . . . . . . . 113, 357, 360 ddi bit . . . . . . . . . . . . . . . . . . . . . . . . 299 ddie bit . . . . . . . . . . . . . . . . . . . . . . 308 deactivation . . . . . . . . . . . . . . . . . . . 155 delay between iom-2 and s . . . . . . 136 design bits . . . . . . . . . . . . . . . . . . . 279 detach detection . . . . . . . . . . . . . . . . 102 device registers . . . . . . . . . . . . . . . . 106 dfu - device firmware upgrade . . . 331 dgsr register . . . . . . . . . . . . . . . . . 117 dier register . . . . . . . . . . . . . . . . . . 308 dim2-0 bits . . . . . . . . . . . . . . . . . . . . 232 dinit bit . . . . . . . . . . . . . . . . . . . . . . 113 diom_inv bit . . . . . . . . . . . . . . . . . . 271 diom_sds bit . . . . . . . . . . . . . . . . . 271 dirn bit . . . . . . . . . . . . . . . . . . . . . . . 120 dirr register . . . . . . . . . . . . . . . . . . 299 dis_iom bit . . . . . . . . . . . . . . . . . . . 268 dis_od bit . . . . . . . . . . . . . . . . . . . . 268 dis_tr bit . . . . . . . . . . . . . . . . . . . . 244 dis_tx bit . . . . . . . . . . . . . . . . . . . . 246 dnrien bit . . . . . . . . . . . . . . . . . . . . 309 dnrn bit . . . . . . . . . . . . . . . . . . . . . . 301 donen bit . . . . . . . . . . . . . . . . . . . . 120 download mode . . . . . . . . . . . 318, 323 dpl / dph registers . . . . . . . . . . . . . . 61 dprio bit . . . . . . . . . . . . . . . . . . . . . 248 dps bit . . . . . . . . . . . . . . . . . . 258, 266 dps_ci1 bit . . . . . . . . . . . . . . . . . . . 264 dps_d bit . . . . . . . . . . . . . . . . . . . . . 263 dpsel register . . . . . . . . . . . . . . . . . . 60 dpwdr register . . . . . . . 115, 360, 361 drvi bit . . . . . . . . . . . . . . . . . . . . . . 304 drvie bit . . . . . . . . . . . . . . . . . . . . . 310 dsir register . . . . . . . . . . . . . . . . . . 301 dsiz register . . . . . . . . . . . . . . 70, 358 dst15-2 bits . . . . . . . . . . . . . . . . . . . 117 dual buffer mode . . . . . . . . . . . . 77, 84 psb 2154 data sheet 393 2001-01-24 e ea1 bit . . . . . . . . . . . . . . . . . . . . . . . 238 ea2 bit . . . . . . . . . . . . . . . . . . . . . . . 238 eal bit . . . . . . . . . . . . . . . . . . . . . . . 306 eale bit . . . . . . . . . . . . . . . . . . . . . . . 71 eaw bit . . . . . . . . . . . . . . . . . . . . . . 276 eepadr register . . . . . . . . . . . . . . . 354 eepcmd register . . . . . . . . . . . . . . 353 eepdat register . . . . . . . . . . . . . . . 354 eepint register . . . . . . . . . . . . . . . . 299 eeprom . . . . . . . . . . . . . . . . . . . . . 337 eepsl register . . . . . . . . . . . . . . . . 355 egsr register . . . . . . . . . . . . . . . . . 124 el1/0 bits . . . . . . . . . . . . . . . . . . . . . 254 eld bit . . . . . . . . . . . . . . . . . . . . . . . 355 electrical characteristics . . . . . . . . . 369 emulation . . . . . . . . . . . . . . . . . . . 45, 49 en_b2/1r bits . . . . . . . . . . . . . . . . . 261 en_b2/1x bits . . . . . . . . . . . . . . . . . 261 en_bc2/1 bits . . . . . . . . . . . . . . . . . 263 en_bcl bit . . . . . . . . . . . . . . . . . . . 268 en_ci1 bit . . . . . . . . . . . . . . . . . . . . 264 en_d bit . . . . . . . . . . . . . . . . . 261, 263 en_i0 bit . . . . . . . . . . . . . . . . . . . . . 260 en_i1 bit . . . . . . . . . . . . . . . . . . . . . 260 en_icv bit . . . . . . . . . . . . . . . . . . . . 244 en_mon bit . . . . . . . . . . . . . . . . . . . 266 en_o0 bit . . . . . . . . . . . . . . . . . . . . 260 en_o1 bit . . . . . . . . . . . . . . . . . . . . 260 en_sfsc bit . . . . . . . . . . . . . . . . . . 245 en_tbm bit . . . . . . . . . . . . . . . . . . . 260 endpoint registers . . . . . . . . . . . . . . 106 enhanced hooks . . . . . . . . . . . . . . . . 49 ens_tssx bits . . . . . . . . . . . . . . . . 267 enumeration . . . . . . . . . . . . . . . . . . . 96 eodien bit . . . . . . . . . . . . . . . . . . . . 309 eodn bit . . . . . . . . . . . . . . . . . . . . . 301 epban register . . . . . . . . . . . . . . . . 122 epbcn register . . . . . . . . . . . . 119, 310 epbsn register . . . . . . . . . . . . . . . . 120 epcint bit . . . . . . . . . . . . . . . . . . . . 299 epi7-0 bits . . . . . . . . . . . . . . . . . . . . 303 epien register . . . . . . . . . . . . . . . . . 309 epirn register . . . . . . . . . . . . . . . . . 301 eplenn register . . . . . . . . . . . . . . . . 123 eprom . . . . . . . . . . . . . . . . . . . . . . 329 eprom mode . . . . . . . . . . . . . . . . . 318 eps7, 2-0 bits . . . . . . . . . . . . . . . . . . 108 epsel register . . . . . . . . . . . . . . . . . 108 epst7-0 bits . . . . . . . . . . . . . . . . . . 107 es bit . . . . . . . . . . . . . . . . . . . . . . . . 306 espn bit . . . . . . . . . . . . . . . . . . . . . . 120 est15-1 bits . . . . . . . . . . . . . . . . . . . 124 esta bit . . . . . . . . . . . . . . . . . . . . . . 355 et1/0 bits . . . . . . . . . . . . . . . . . . . . . 306 ewpd bit . . . . . . . . . . . . . . . . . . . . . . 64 ex11-6 . . . . . . . . . . . . . . . . . . . . . . . 307 ex14-12 bits . . . . . . . . . . . . . . . . . . . 307 ex5/0 bits . . . . . . . . . . . . . . . . . . . . . 306 exlp bit . . . . . . . . . . . . . . . . . . . . . . 244 exmb register . . . . . . . . . . . . . . . . . 286 exmd1 register . . . . . . . . . . . . . . . . 234 extended transparent mode . . . . . . . 214 external bus interface . . . . . . . . . . . . . 40 external memory address mapping . . 30 f fbs bit . . . . . . . . . . . . . . . . . . . . . . . 254 features . . . . . . . . . . . . . . . . . . . . . . . . 4 firmware . . . . . . . . . . . . . . . . . . . . . . 318 download mode . . . . . . . . . . . . 323 execution in external eprom . . 329 execution in ram . . . . . . 324, 325 operation modes . . . . . . . 318, 357 switching execution from rom to ram . . . . . . . . . . . . . . . 358 fnrh/l registers . . . . . . . . . . . . . . . 116 fsyn bit . . . . . . . . . . . . . . . . . . . . . . 247 psb 2154 data sheet 394 2001-01-24 g gate1/0 bits . . . . . . . . . . . . . . . . . . . 58 general features . . . . . . . . . . . . . . . 340 general purpose registers . . . . . . . . . 32 gepien bit . . . . . . . . . . . . . . . . 119, 310 gepir register . . . . . . . . . . . . . . . . . 303 gesr register . . . . . . . . . . . . . . . . . 107 gf1/0 bits . . . . . . . . . . . . . . . . . . . . . 62 gf3/2 bits . . . . . . . . . . . . . . . . . . . . . 63 global registers . . . . . . . . . . . . . . . . 106 gsie bit . . . . . . . . . . . . . . . . . . . . . . 301 gsir bit . . . . . . . . . . . . . . . . . . . . . . 301 h ha1/0 bits . . . . . . . . . . . . . . . . . . . . 290 hardware reset . . . . . . . . . . . . . . . . 344 hcon register . . . . . . . . . . . . . . 65, 357 hdlc controllers access to iom channels . . . . . . 213 data reception . . . . . . . . . . . . . 199 data transmission . . . . . . . . . . . 208 extended transparent mode . . . 214 interrupts . . . . . . . . . . . . . . . . . 215 receive frame structure . . . . . . 206 test functions . . . . . . . . . . . . . . 216 transmit frame structure . . . . . 213 high power device . . . . . . . . . . . . . . 339 i ica/b bits . . . . . . . . . . . . . . . . . 275, 305 icd bit . . . . . . . . . . . . . . . . . . . 275, 305 icv bit . . . . . . . . . . . . . . . . . . . . . . . 247 id register . . . . . . . . . . . . . . . . . . . . 279 idle bit . . . . . . . . . . . . . . . . . . . . . . . 62 idle mode . . . . . . . . . . . . . . . . . . . . . 359 idle to active . . . . . . . . . . . . . . . . . . . 366 idls bit . . . . . . . . . . . . . . . . . . . . . . . 62 idsl . . . . . . . . . . . . . . . . . . . . . . . . . 171 ie0 bit . . . . . . . . . . . . . . . . . . . . . 57, 298 ien0 register . . . . . . . . . . . . . . . . . . 306 ien1 register . . . . . . . . . . . . . . . . . . . 307 ien2 register . . . . . . . . . . . . . . . . . . . 307 if1/0 bits . . . . . . . . . . . . . . . . . . . . . . 109 ifc1-0 bits . . . . . . . . . . . . . . . . . . . . 112 ifcsel register . . . . . . . . . . . . . . . . 109 igsr register . . . . . . . . . . . . . . . . . . 118 incen bit . . . . . . . . . . . . . . . . . . . . . 119 int1/0 bits . . . . . . . . . . . . . . . . . . . . 276 interrupt enable registers . . . . . . . . . . . . 306 handling . . . . . . . . . . . . . . . . . . 314 priority . . . . . . . . . . . . . . . . . . . . 312 registers . . . . . . . . . . . . . . . . . . 298 system . . . . . . . . . . . . . . . . . . . 293 vectors . . . . . . . . . . . . . . . . . . . 314 interrupt input . . . . . . . . . . . . . . . . . . 349 interrupt transfer . . . . . . . . . . . . . . . . . 76 interrupt wakeup control . . . . . . . . . . 368 iom_cr register . . . . . . . . . . . . . . . . 268 iom-2 . . . . . . . . . . . . . . . . . . . . . . . . 158 frame structure (te) . . . . . . . . . 159 handler . . . . . . . . . . . . . . . . . . . 160 interface timing . . . . . . . . . . . . . 377 monitor channel . . . . . . . . . . . . . 177 ip0/1 registers . . . . . . . . . . . . . . . . . 313 isdn module power down . . . . . . . . 363 isochronous transfer . . . . . . . . . . . . . . 76 ist15-0 bits . . . . . . . . . . . . . . . . . . . 118 ista register . . . . . . . . . . . . . . 275, 305 ista_init register . . . . . . . . . . . . . . 276 istab register . . . . . . . . . . . . . . . . . 281 istad register . . . . . . . . . . . . . . . . . 228 istatr register . . . . . . . . . . . . . . . . 251 it0 bit . . . . . . . . . . . . . . . . . . . . 57, 298 itf bit . . . . . . . . . . . . . . . . . . . 234, 286 j jitter . . . . . . . . . . . . . . . . . . . . . . . . . 343 psb 2154 data sheet 395 2001-01-24 l l1sw bit . . . . . . . . . . . . . . . . . . . . . 244 la bit . . . . . . . . . . . . . . . . . . . . . . . . 290 ld bit . . . . . . . . . . . . . . . . . . . . 247, 251 ldd bit . . . . . . . . . . . . . . . . . . . . . . . 244 led bit . . . . . . . . . . . . . . . . . . . . . . . 254 led output . . . . . . . . . . . . . . . . . . . . 128 level detection . . . . . . . . . . . . . . . . . 142 ln6-0 bits . . . . . . . . . . . . . . . . . . . . . 123 lock bit . . . . . . . . . . . . . . . . . . . . . . 66 logic symbol . . . . . . . . . . . . . . . . . . . . 7 looping data . . . . . . . . . . . . . . . . . . 163 low power device . . . . . . . . . . . . . . 339 lp_a bit . . . . . . . . . . . . . . . . . . . . . . 248 m m1/0 bits . . . . . . . . . . . . . . . . . . . . . . 58 m3-0 bits . . . . . . . . . . . . . . . . . . . . . . 66 mab bit . . . . . . . . . . . . . . . . . . . . . . 273 mac bit . . . . . . . . . . . . . . . . . . . . . . 274 mask register . . . . . . . . . . . . . . . . . 311 maskb register . . . . . . . . . . . . . . . . 282 maskd register . . . . . . . . . . . . . . . . 229 masktr register . . . . . . . . . . . . . . . 252 m-bit synchronisation . . . . . . . . . . . 135 mcda register . . . . . . . . . . . . . . . . . 272 mcdaxy bits . . . . . . . . . . . . . . . . . . 272 mconf register . . . . . . . . . . . . . . . . 274 mda bit . . . . . . . . . . . . . . . . . . . . . . 273 mdr bit . . . . . . . . . . . . . . . . . . . . . . 273 mds2-0 bits . . . . . . . . . . . . . . . 232, 285 memory access enable . . . . . . . . . . . . . 357 configurations . . . . . . . . . . . . . 322 control signal switching . . . . . . 358 extension . . . . . . . . . . . . . . . . . 325 organisation . . . . . . . . . . . . . . . . 29 partitioning . . . . . . . . . . . . . . . . 358 memory buffer address generation . . . . . . . . . . . 93 modes . . . . . . . . . . . . . . . . . . . . . 77 organisation . . . . . . . . . . . . . . . . 91 memory interface timing emulation mode . . . . . . . . . . . . 382 normal mode . . . . . . . . . . . . . . . 379 mer bit . . . . . . . . . . . . . . . . . . . . . . . 273 mfen bit . . . . . . . . . . . . . . . . . 249, 250 mha bit . . . . . . . . . . . . . . . . . . 236, 287 microcontroller . . . . . . . . . . . . . . . . . . 27 registers . . . . . . . . . . . . . . . . . . . 59 reset . . . . . . . . . . . . . . . . . . . . . 344 mie bit . . . . . . . . . . . . . . . . . . . . . . . 273 mla bit . . . . . . . . . . . . . . . . . . 236, 287 mmod bit . . . . . . . . . . . . . . . . . . . . . . 65 mocr register . . . . . . . . . . . . . . . . . 273 mode1 register . . . . . . . . . . . 277, 363 mode2-0 bits . . . . . . . . . . . . . . . . . . 253 modeb register . . . . . . . . . . . . . . . . 285 moded register . . . . . . . . . . . . . . . . 232 mon_cr register . . . . . . . . . . . . . . . 266 monitor channel error treatment . . . . . . . . . . . . . 181 handshake procedure . . . . . . . . 178 interrupt logic . . . . . . . . . . . . . . . 184 master device . . . . . . . . . . . . . . 183 time-out procedure . . . . . . . . . . 183 monitoring data . . . . . . . . . . . . . . . . . 167 monitoring tic bus . . . . . . . . . . . . . . 167 mor register . . . . . . . . . . . . . . . . . . 272 mos bit . . . . . . . . . . . . . . . . . . 275, 305 mosr register . . . . . . . . . . . . . . . . . 273 mox register . . . . . . . . . . . . . . . . . . 272 mrc bit . . . . . . . . . . . . . . . . . . . . . . . 273 mre bit . . . . . . . . . . . . . . . . . . . . . . . 273 msta register . . . . . . . . . . . . . . . . . . 274 msti register . . . . . . . . . . . . . . . . . . 270 msyn bit . . . . . . . . . . . . . . . . . . . . . 249 multiframe synchronization . . . . . . . . 135 psb 2154 data sheet 396 2001-01-24 multiframing . . . . . . . . . . . . . . . . . . . 133 mxc bit . . . . . . . . . . . . . . . . . . . . . . 273 n n4-0 bits . . . . . . . . . . . . . . . . . . . . . . 66 nackn bit . . . . . . . . . . . . . . . . . . . . 301 naien bit . . . . . . . . . . . . . . . . . . . . . 309 nodien bit . . . . . . . . . . . . . . . . . . . . 309 nodn bit . . . . . . . . . . . . . . . . . . . . . 301 o od7-0 bits . . . . . . . . . . . . . . . . . . . . 254 oe7-0 bits . . . . . . . . . . . . . . . . . . . . 256 operational description . . . . . . . . . . 357 oscillator . . . . . . . . . . . . . . . . . . . . . 374 ov bit . . . . . . . . . . . . . . . . 63, 237, 289 overflow (usb buffer) . . . . . . . . . . . . 90 overview . . . . . . . . . . . . . . . . . . . . . . . 3 p p bit . . . . . . . . . . . . . . . . . . . . . . . . . . 63 package outlines . . . . . . . . . . . . . . . 390 pagen bit . . . . . . . . . . . . . . . . . . . . 122 pclk bit . . . . . . . . . . . . . . . . . . . . . . . 66 pcon register . . . . . . . . . 62, 359, 361 pd bit . . . . . . . . . . . . . . . . . . . . . . . . 248 pds bit . . . . . . . . . . . . . . . . . . . . . . . 246 pin description . . . . . . . . . . . . . . . . . . 13 plcona/b registers . . . . . . . . . 66, 357 plconb register . . . . . . . . . . . . . . . 361 pll configuration . . . . . . . . . . . . . . . 357 port structures . . . . . . . . . . . . . . . . . . 47 power management . . . . . . . . . . . . . 339 power saving modes . . . . . . . . . . . . 359 program memory . . . . . . . . . . . . . . . . 32 pscen bit . . . . . . . . . . . . . . . . . . . . . 66 pscval bit . . . . . . . . . . . . . . . . . . . . 66 psiz register . . . . . . . . . . . . . . . 69, 358 pstat bit . . . . . . . . . . . . . . . . . . . . 117 psw register . . . . . . . . . . . . . . . . . . . 63 r rab bit . . . . . . . . . . . . . . . . . . 239, 290 rac bit . . . . . . . . . . . . . . . . . . 232, 285 raci bit . . . . . . . . . . . . . . . . . 230, 283 rah1 register . . . . . . . . . . . . . . . . . . 287 rah2 register . . . . . . . . . . . . . . . . . . 287 ral1 register . . . . . . . . . . . . . . . . . . 289 ral2 register . . . . . . . . . . . . . . . . . . 290 ram partitioning . . . . . . . . . . . . . . . . 358 random access . . . . . . . . . . . . . . . . . 77 rbc11-8 bits . . . . . . . . . . . . . 237, 289 rbc7-0 bits . . . . . . . . . . . . . . 237, 288 rbchb register . . . . . . . . . . . . . . . . 289 rbchd register . . . . . . . . . . . . . . . . 237 rbclb register . . . . . . . . . . . . . . . . . 288 rbcld register . . . . . . . . . . . . . . . . 237 rcrc bit . . . . . . . . . . . . . . . . 234, 286 rdo bit . . . . . . . . . . . . . . . . . . 239, 290 registers interrupt . . . . . . . . . . . . . . . . . . . 298 interrupt enable . . . . . . . . . . . . . 306 interrupt priority . . . . . . . . . . . . . 312 microcontroller . . . . . . . . . . . . . . . 59 spi interface . . . . . . . . . . . . . . . 353 timer 0 and 1 . . . . . . . . . . . . . . . 56 usb . . . . . . . . . . . . . . . . . . . . . . 103 remote wakeup . . . . . . . . . . . . . . . . 338 res_xxx bits . . . . . . . . . . . . . . . . . . 280 reset generation . . . . . . . . . . . . . . . 344 reset output . . . . . . . . . . . . . . 345, 346 reset timing . . . . . . . . . . . . . . . . . . . 389 reset to active . . . . . . . . . . . . . . . . . 365 rfbs bits . . . . . . . . . . . . . . . . 234, 286 rfifob register . . . . . . . . . . . . . . . . 292 rfifod register . . . . . . . . . . . . . . . . 227 rfo bit . . . . . . . . . . . . . . . . . . 228, 281 ric bit . . . . . . . . . . . . . . . . . . . . . . . . 251 rinf bits . . . . . . . . . . . . . . . . . . . . . . 247 rleien bit . . . . . . . . . . . . . . . . . . . . 309 rlen bit . . . . . . . . . . . . . . . . . . . . . . 301 psb 2154 data sheet 397 2001-01-24 rlp bit . . . . . . . . . . . . . . . . . . . . . . . 246 rmc bit . . . . . . . . . . . . . . . . . . 231, 284 rme bit . . . . . . . . . . . . . . . . . . 228, 281 rpf bit . . . . . . . . . . . . . . . . . . . 228, 281 rpll - receive pll . . . . . . . . . . . . 343 rpll_adj bit . . . . . . . . . . . . . . . . . 245 rpwd bit . . . . . . . . . . . . . . . . . . . . . 115 rres bit . . . . . . . . . . . . . . . . . 231, 284 rs1/0 bits . . . . . . . . . . . . . . . . . . . . . 63 rsm bit . . . . . . . . . . . . . . . . . . . . . . 113 rss2/1 bits . . . . . . . . . . . . . . . . . . . 277 rstab register . . . . . . . . . . . . . . . . 290 rstad register . . . . . . . . . . . . . . . . 239 rwup bit . . . . . . . . . . . . . . . . . . . . . 117 s s/g bit . . . . . . . . . . . . . . . . . . . 192, 241 s/t-interface . . . . . . . . . . . . . . . . . . 129 circuitry . . . . . . . . . . . . . . . . . . 140 coding . . . . . . . . . . . . . . . . . . . 131 delay compensation . . . . . . . . . 142 external protection circuitry . . . 140 multiframe synchronization . . . . 135 multiframing . . . . . . . . . . . . . . . 133 receiver characteristics . . . . . . 139 transceiver enable/disable . . . . 143 transmitter characteristics . . . . 138 sa1/0 bits . . . . . . . . . . . . . . . . . . . . 239 sap1 register . . . . . . . . . . . . . . . . . . 236 sap2 register . . . . . . . . . . . . . . . . . . 236 sbi bit . . . . . . . . . . . . . . . . . . . . . . . 299 sbie bit . . . . . . . . . . . . . . . . . . . . . . 308 scs bit . . . . . . . . . . . . . . . . . . . . . . . . 73 sds . . . . . . . . . . . . . . . . . . . . . . . . . 174 sds_bcl bit . . . . . . . . . . . . . . . . . . 271 sds_conf register . . . . . . . . . . . . 271 sds_cr registers . . . . . . . . . . . . . . 267 se0i bit . . . . . . . . . . . . . . . . . . . . . . 299 se0ie bit . . . . . . . . . . . . . . . . . . . . . 308 sei bit . . . . . . . . . . . . . . . . . . . . . . . 299 seie bit . . . . . . . . . . . . . . . . . . . . . . . 308 self-powered mode . . . . . . . . . . . . . 102 separate memory . . . . . . . 40, 322, 328 sequence of operations . . . . . . . . . . 365 sequential access . . . . . . . . . . . . . . . 78 serial data strobe . . . . . . . . . . . . . . . 174 setrdn bit . . . . . . . . . . . . . . . . . . . . 120 setwrn bit . . . . . . . . . . . . . . . . . . . 120 sgd bit . . . . . . . . . . . . . . . . . . . . . . . 246 sgp bit . . . . . . . . . . . . . . . . . . . . . . . 246 shared memory . . . . . . . . 40, 322, 325 shifting data . . . . . . . . . . . . . . . . . . . 163 single buffer mode . . . . . . . . . . . 77, 79 single-chip mode . . . . . . . . . . . . . . . 324 slip bit . . . . . . . . . . . . . . . . . . . . . . . 247 sme bit . . . . . . . . . . . . . . . . . . . . . . . . 62 sms bit . . . . . . . . . . . . . . . . . . . . . . . . 62 sodien bit . . . . . . . . . . . . . . . . . . . . 309 sodn bit . . . . . . . . . . . . . . . . . . . . . . 301 sofden bit . . . . . . . . . . . . . . . . . . . 119 sofi bit . . . . . . . . . . . . . . . . . . . . . . 299 sofie bit . . . . . . . . . . . . . . . . . . . . . 308 software reset . . . . . . . . . . . . . . . . . 344 special function registers . . . . . . . . . . 33 spi interface . . . . . . . . . . . . . . . . . . . 350 registers . . . . . . . . . . . . . . . . . . 353 timing . . . . . . . . . . . . . . . . . . . . 387 spu bit . . . . . . . . . . . . . . . . . . . . . . . 268 sqc bit . . . . . . . . . . . . . . . . . . . . . . . 251 sqr11-14 bits . . . . . . . . . . . . . . . . . 249 sqr21-24 bits . . . . . . . . . . . . . . . . . 250 sqr31-34 bits . . . . . . . . . . . . . . . . . 250 sqr41-44 bits . . . . . . . . . . . . . . . . . 251 sqr51-54 bits . . . . . . . . . . . . . . . . . 251 sqrr1 register . . . . . . . . . . . . . . . . 249 sqrr2 register . . . . . . . . . . . . . . . . 250 sqrr3 register . . . . . . . . . . . . . . . . 251 sqw bit . . . . . . . . . . . . . . . . . . . . . . 251 sqx11-14 bits . . . . . . . . . . . . . . . . . 250 sqxr1 register . . . . . . . . . . . . . . . . 250 psb 2154 data sheet 398 2001-01-24 sra bit . . . . . . . . . . . . . . . . . . . 234, 286 sres register . . . . . . . . . . . . . . . . . 280 st bit . . . . . . . . . . . . . . . . . . . . 275, 305 stall bit . . . . . . . . . . . . . . . . . . . . . 124 stalln bit . . . . . . . . . . . . . . . . . . . . 119 standard command registers . . . . . . 106 standard device request . . . . . . . . . . 97 starb register . . . . . . . . . . . . . . . . 283 stard register . . . . . . . . . . . . . . . . 230 stat0 bit . . . . . . . . . . . . . . . . . . . . . . 71 stat2/1 bits . . . . . . . . . . . . . . . . . . . 73 state machine te and lt-t mode . . . . . . . . . . 148 sti bit . . . . . . . . . . . . . . . . . . . 231, 299 sti register . . . . . . . . . . . . . . . . . . . 269 stie bit . . . . . . . . . . . . . . . . . . . . . . 308 stixy bits . . . . . . . . . . . . . . . . . 269, 270 stop/go bit . . . . . . . . . . . . . . . . . . . . 192 stovxy bits . . . . . . . . . . . . . . . 269, 270 strobed data clock . . . . . . . . . . . . . . 174 sui bit . . . . . . . . . . . . . . . . . . . . . . . 299 suie bit . . . . . . . . . . . . . . . . . . . . . . 308 susp bit . . . . . . . . . . . . . . . . . . . . . 113 suspend mode . . . . . . . . . . . . . . . . . 361 suspend to active . . . . . . . . . . . . . . 367 svn4-0 bits . . . . . . . . . . . . . . . . . . . . 65 swap bit . . . . . . . . . . . . . . . . . . . . . 260 swck bit . . . . . . . . . . . . . . . . . . . . . . 66 switching of control signals . . . . . . . . 41 swr bit . . . . . . . . . . . . . . . . . . . . . . 113 synchronous transfer . . . . . . . . . . . . 168 syscon1 register . . . . . . . . . . . 71, 357 syscon2 register . . . . . . . . . . . 73, 358 system identification . . . . . . . . . . . . 321 t ta bit . . . . . . . . . . . . . . . . . . . . . . . . 239 tba2-0 bits . . . . . . . . . . . . . . . . . . . 242 tcon register . . . . . . . . . . . . . . 57, 298 tddis bit . . . . . . . . . . . . . . . . . . . . . 248 tei1 register . . . . . . . . . . . . . . . . . . . 238 tei2 register . . . . . . . . . . . . . . . . . . . 238 test functions . . . . . . . . . . . . . . . . . . 143 test signals . . . . . . . . . . . . . . . . . . . 217 tf1/0 bits . . . . . . . . . . . . . . . . . 57, 298 th1/0 bits . . . . . . . . . . . . . . . . . . . . . . 56 tic bus . . . . . . . . . . . . . . . . . . . . . . . 188 tic_dis bit . . . . . . . . . . . . . . . . . . . . 268 timer 0 and 1 . . . . . . . . . . . . . . . . . . . 51 mode 0 . . . . . . . . . . . . . . . . . . . . 52 mode 1 . . . . . . . . . . . . . . . . . . . . 53 mode 2 . . . . . . . . . . . . . . . . . . . . 54 mode 3 . . . . . . . . . . . . . . . . . . . . 55 registers . . . . . . . . . . . . . . . . . . . 56 timer 2 and 3 . . . . . . . . . . . . . . . . . . 126 timr1 register . . . . . . . . . . . . . . . . . 235 timr2 register . . . . . . . . . . . . . . . . . 280 tin2/1 bits . . . . . . . . . . . . . . . . . . . . 276 tl/th registers . . . . . . . . . . . . . . . . . . 56 tl1/0 bits . . . . . . . . . . . . . . . . . . . . . . 56 tlp bit . . . . . . . . . . . . . . . . . . 240, 291 tmb register . . . . . . . . . . . . . . . . . . . 291 tmd bit . . . . . . . . . . . . . . . . . . . . . . . 280 tmd register . . . . . . . . . . . . . . . . . . . 240 tmod register . . . . . . . . . . . . . . . . . . 58 tout bit . . . . . . . . . . . . . . . . . . . . . . 274 tpwd bit . . . . . . . . . . . . . . . . . . . . . 115 tr_cmd register . . . . . . . . . . 248, 363 tr_conf0 register . . . . . . . . 244, 363 tr_conf1 register . . . . . . . . . . . . . 245 tr_conf2 register . . . . . . . . . . . . . 246 tr_cr register . . . . . . . . . . . . . . . . . 261 tr_mode register . . . . . . . . . . . . . . 253 tr_sta register . . . . . . . . . . . . . . . . 247 tr_tsdp_bc1/2 registers . . . . . . . 258 tr1/0 bits . . . . . . . . . . . . . . . . . 57, 298 tran bit . . . . . . . . . . . . . . . . . 275, 305 transceiver enable/disable . . . . . . . . 143 transfer modes . . . . . . . . . . . . . . . . . 76 transformer specification . . . . . . . . . 375 psb 2154 data sheet 399 2001-01-24 tss bits . . . . . . . . . . . . . . . . . . 258, 267 u ubfm bit . . . . . . . . . . . . . . . . . . . . . 120 uclk bit . . . . . . . . . . . . . . . . . . . . . 113 underrun (usb buffer) . . . . . . . . . . . . 90 usb buffer underrun/overflow . . . . . . 90 cdc . . . . . . . . . . . . . . . . . . . . . 331 clock enable . . . . . . . . . . . 340, 357 configuration block . . . . . . . . . . . 94 configuration data . . . . . . . . . . 334 device framework . . . . . . . . . . . . 96 dfu . . . . . . . . . . . . . . . . . . . . . 331 general model . . . . . . . . . . . . . 330 initialization . . . . . . . . . . . . . . . . . 94 models . . . . . . . . . . . . . . . . . . . 330 module . . . . . . . . . . . . . . . . . . . . 75 power modes . . . . . . . . . . . . . . 102 receiver power down . . . . . . . . 360 registers . . . . . . . . . . . . . . . . . 103 reset . . . . . . . . . . . . . . . . . . . . 344 transceiver . . . . . . . . . . . . . . . . 100 transceiver characteristics . . . . 388 transfer modes . . . . . . . . . . . . . 76 transmitter power down . . . . . . 360 usbval register . . . . . . . . . . . . . . . 110 v value bits . . . . . . . . . . . . . . . . . . . 235 vfr bit . . . . . . . . . . . . . . . . . . . 239, 290 voltage regulator . . . . . . . . . . . . . . 372 voltage regulator . . . . . . . . . . . . . . . 356 w wake up . . . . . . . . . . . . . . . . . . . . . . 363 watchdog . . . . . . . . . . . . . . . . . . . . . 345 wcon register . . . . . . . . . . . . . . . . . . 64 wov bit . . . . . . . . . . . . . . . . . . . . . . 276 wpci bit . . . . . . . . . . . . . . . . . . . . . . . 64 wpi0 bit . . . . . . . . . . . . . . . . . . . . . . . 64 wptr bit . . . . . . . . . . . . . . . . . . . . . . 64 wpus bit . . . . . . . . . . . . . . . . . . . . . . 64 wtc1/2 bits . . . . . . . . . . . . . . . . . . . 277 x xaci bit . . . . . . . . . . . . . . . . . 230, 283 xcrc bit . . . . . . . . . . . . . . . . . 234, 286 xdov bit . . . . . . . . . . . . . . . . . 230, 283 xdu bit . . . . . . . . . . . . . . . . . . 228, 281 xfbs bit . . . . . . . . . . . . . . . . . 234, 286 xfifob register . . . . . . . . . . . . . . . . 292 xfifod register . . . . . . . . . . . . . . . . 227 xfw bit . . . . . . . . . . . . . . . . . . 230, 283 xinf bits . . . . . . . . . . . . . . . . . . . . . . 248 xmap1/0 bits . . . . . . . . . . . . . . . . . . . 71 xme bit . . . . . . . . . . . . . . . . . . 231, 284 xmr bit . . . . . . . . . . . . . . . . . . . . . . . 228 xpage register . . . . . . . . . . . . . . . . . 74 xpr bit . . . . . . . . . . . . . . . . . . 228, 281 xram access enable/disable . . . . . . . 42 xres bit . . . . . . . . . . . . . . . . . 231, 284 xtf bit . . . . . . . . . . . . . . . . . . 231, 284 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ? business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction. ? dr. ulrich schumacher |
Price & Availability of PSB2154-HV13
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |